CERN Accelerating science

ATLAS Note
Report number ATL-DAQ-PROC-2013-035
Title Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
Related titleHardware, firmware and software developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
Author(s)

Anders, G (Ruprecht-Karl U. ; CERN) ; Bertelsen, H (Bohr Inst.) ; Boisen, A (Bohr Inst.) ; Childers, T (Ruprecht-Karls U. ; CERN) ; Dam, M (Bohr Inst.) ; Ellis, N (CERN) ; Farthouat, P (CERN) ; Gabaldon Ruiz, C (CERN) ; Ghibaudi, M (Pisa U. ; CERN) ; Gorini, B (CERN) ; Haas, S (CERN) ; Kaneda, M (CERN) ; Ohm, C (CERN) ; Silva Oliveira, M (Juiz de Fora U. ; CERN) ; Pauly, T (CERN) ; Pottgen, R (Mainz U. ; CERN) ; Schmieden, K (CERN) ; Spiwoks, R (CERN) ; Xella, S (Bohr Inst.)

Publication 2014
Imprint 02 Nov 2013
Number of pages 10
In: JINST 9 (2014) C01035
In: Topical Workshop on Electronics for Particle Physics, Perugia, Italy, 23 - 27 Sep 2013, pp.C01035
DOI 10.1088/1748-0221/9/01/C01035
Subject category Detectors and Experimental Techniques
Accelerator/Facility, Experiment CERN LHC ; ATLAS
Free keywords Trigger concepts and systems (hardware and software) ; Digital electronics circuits
Abstract The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.
Copyright/License publication: © 2014-2024 CERN (License: CC-BY-3.0)

Corresponding record in: INSPIRE


 Záznam vytvorený 2013-11-02, zmenený 2022-08-10


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