CERN Accelerating science

ATLAS Slides
Report number	ATL-DAQ-SLIDE-2012-359
Title	A Hardware Track Finder for ATLAS Trigger
Author(s)	Volpi, G ; Andreani, A ; Andreazza, A ; Citterio, M ; Favareto, A ; Liberali, V ; Meroni, C ; Riva, M ; Sabatini, F ; Stabile, A ; Annovi, A ; Beretta, M ; Castegnaro, A ; Bevacqua, V ; Crescioli, F ; Francesco, C ; Dell'Orso, M ; Giannetti, P ; Magalotti, D ; Piendibene, M ; Roda, C ; Sacco, I ; Tripiccione, R ; Fabbri, L ; Franchini, M ; Giorgi, F ; Giannuzzi, F ; Lasagni, F ; Sbarra, C ; Valentinetti, S ; Villa, M ; Zoccoli, A ; Lanza, A ; Negri, A ; Vercesi, V ; Bogdan, M ; Boveia, A ; Canelli, F ; Cheng, Y ; Dunford, M ; Li, H L ; Kapliy, A ; Kim, Y K ; Melachrinos, C ; Shochet, M ; Tang, F ; Tang, J ; Tuggle, J ; Tompkins, L ; Webster, J ; Atkinson, M ; Cavaliere, V ; Chang, P ; Kasten, M ; McCarn, A ; Neubauer, M ; Hoff, J ; Liu, T ; Okumura, Y ; Olsen, J ; Penning, B ; Todri, A ; Wu, J ; Drake, G ; Proudfoot, J ; Zhang, J ; Blair, R ; Anderson, J ; Auerbach, B ; Blazey, G ; Kimura, N ; Yorita, K ; Sakurai, Y ; Mitani, T ; Iizawa, T
Corporate author(s)	The ATLAS collaboration
Submitted to	18th IEEE Real-Time Conference 2012, Berkeley, California, 11 - 15 Jun 2012
Submitted by	[email protected] on 08 Jun 2012
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Abstract	The existing three level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~400 Hz for permanent storage at the LHC design luminosity of 10^34 cm^-2 s^-1. When the LHC reaches beyond the design luminosity, the load on the Level-2 trigger system will significantly increase due to both the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast TracKer (FTK) is a custom electronics system that will operate at the full Level-1 accepted rate of 100 KHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories and FPGAs. The performance in important physics areas including b-tagging, tau-tagging and lepton isolation will be demonstrated with the ATLAS MC simulation at different LHC luminosities. The system design will be overviewed. The latest R&D progress of individual components will be presented and related technologies will be discussed.