| Article | |
| Title | An FPGA-based Emulation of the G-Link Chip-Set for the ATLAS Level-1 Barrel Muon Trigger |
| Author(s) | Aloisio, A (INFN, Naples) ; Cevenini, F (INFN, Naples ; Naples U.) ; Giordano, R (INFN, Naples ; Naples U.) ; Izzo, V (INFN, Naples) |
| Publication | CERN, 2009 |
| In: | Proceedings of the Topical Workshop on Electronics for Particle Physics, pp.509-513 |
| DOI | 10.5170/CERN-2009-006.509 |
| Subject category | Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Abstract | Many High Energy Physics experiments based their serial links on the Agilent HDMP-1032/34A serializer/deserializer chip-set (or GLink). This success was mainly due to the fact that this pair of chips was able to transfer data at ∼ 1 Gb/s with a deterministic latency, fixed after each power up or reset of the link. Despite this unique timing feature, Agilent discontinued the production and no compatible commercial off-the-shelf chip-sets are available. The ATLAS Level-1 Muon trigger includes some serial links based on GLink in order to transfer data from the detector to the counting room. The transmission side of the links will not be upgraded, however a replacement for the receivers in the counting room in case of failures is needed. In this paper, we present a solution to replace GLink transmitters and/or receivers. Our design is based on the gigabit serial IO (GTP) embedded in a Xilinx Virtex 5 Field Programmable Gate Array (FPGA).We present the architecture and we discuss parameters of the implementation such as latency and resource occupation. We compare the GLink chip-set and the GTP-based emulator in terms of latency, eye diagram and power dissipation. |
Corresponding record in: Inspire
Δημιουργία εγγραφής 2010-02-03, τελευταία τροποποίηση 2018-02-09
