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authorTom Lane2009-07-27 05:31:05 +0000
committerTom Lane2009-07-27 05:31:05 +0000
commitbd24c2f8fe750ea8e32f6a4470c5f382a8106f6b (patch)
treeef75aaca7f4afba4e5549fff1d1c0c76dd70ba63
parenteb9f071a04ae43cb1e7bd7c53bb3aeb2ad44e1ae (diff)
Add s_lock support for SuperH architecture.
After a patch originally submitted by Nobuhiro Iwamatsu, but corrected (I think) to match our guidelines for safe use of asm fragments. This should be considered untested ...
-rw-r--r--src/include/storage/s_lock.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
index dceceba851..48208b9db7 100644
--- a/src/include/storage/s_lock.h
+++ b/src/include/storage/s_lock.h
@@ -568,6 +568,36 @@ typedef int slock_t;
#endif /* __m32r__ */
+#if defined(__sh__) /* Renesas' SuperH */
+#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
+#define TAS(lock) tas(lock)
+
+static __inline__ int
+tas(volatile slock_t *lock)
+{
+ register int _res;
+
+ /*
+ * This asm is coded as if %0 could be any register, but actually SuperH
+ * restricts the target of xor-immediate to be R0. That's handled by
+ * the "z" constraint on _res.
+ */
+ __asm__ __volatile__(
+ " tas.b @%2 \n"
+ " movt %0 \n"
+ " xor #1,%0 \n"
+: "=z"(_res), "+m"(*lock)
+: "r"(lock)
+: "memory", "t");
+ return _res;
+}
+
+#endif /* __sh__ */
+
+
/* These live in s_lock.c, but only for gcc */