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authorThomas Munro2021-03-12 02:24:28 +0000
committerThomas Munro2021-03-12 02:36:16 +0000
commit43c66624964aa1d2f519ad6be0c5ea8f170cf357 (patch)
tree7e47935e87be9215b643592ebef25dd4a7540d0e
parent7bb97211a5589265f3f88183ae9353639ab184c6 (diff)
Minor modernization for README.barrier.
Itanium is very uncommon and being discontinued. ARM is everywhere. Prefer ARM as an example of an architecture with weak memory ordering.
-rw-r--r--src/backend/storage/lmgr/README.barrier2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/backend/storage/lmgr/README.barrier b/src/backend/storage/lmgr/README.barrier
index 4e37a4acbe..e73d6799ab 100644
--- a/src/backend/storage/lmgr/README.barrier
+++ b/src/backend/storage/lmgr/README.barrier
@@ -38,7 +38,7 @@ Surprisingly, however, the second backend could also end up with foo = 0
and bar = 1. The compiler might swap the order of the two stores performed
by the first backend, or the two loads performed by the second backend.
Even if it doesn't, on a machine with weak memory ordering (such as PowerPC
-or Itanium) the CPU might choose to execute either the loads or the stores
+or ARM) the CPU might choose to execute either the loads or the stores
out of order. This surprising result can lead to bugs.
A common pattern where this actually does result in a bug is when adding items