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CERN Document Server 15 záznamov nájdených  1 - 10ďalší  skoč na záznam: Hľadanie trvalo 0.67 sekúnd. 
1.
Strategies and performance of the CMS silicon tracker alignment during LHC Run 2 / CMS Collaboration
The strategies for and the performance of the CMS silicon tracking system alignment during the 2015-2018 data-taking period of the LHC are described. The alignment procedures during and after data taking are explained. [...]
arXiv:2111.08757; CMS-TRK-20-001; CERN-EP-2021-203; CMS-TRK-20-001-003.- Geneva : CERN, 2022-08-11 - 45 p. - Published in : Nucl. Instrum. Methods Phys. Res., A 1037 (2022) 166795 Fulltext: 2111.08757 - PDF; Publication - PDF; fermilab-pub-21-673-cms - PDF; Fulltext from Publisher: PDF; External link: Fermilab Library Server
2.
Algorithms for Threshold Dispersion Minimization of the CHIPIX65 Asynchronous Front-End / Sonzogni, Mauro ; De Canio, Francesco ; Gaioni, Luigi ; Manghisoni, Massimo ; Re, Valerio ; Traversi, Gianluca ; Ratti, Lodovico
This work discusses four different algorithms for the minimization of threshold dispersion inmultichannel readout circuits for pixel detectors. These algorithms, which are based on differentmethods (e.g. [...]
SISSA, 2019 - 5 p. - Published in : PoS TWEPP2018 (2019) 076
In : Topical Workshop on Electronics for Particle Physics, Antwerp, Belgique, 17 - 21 Sep 2018, pp.076
3.
Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications / De Canio, Francesco (INFN, Pavia) ; Gaioni, Luigi (INFN, Pavia ; Bergamo U.) ; Manghisoni, Massimo (INFN, Pavia ; Bergamo U.) ; Ratti, Lodovico (INFN, Pavia ; Pavia U.) ; Re, Valerio (INFN, Pavia ; Bergamo U.) ; Traversi, Gianluca (INFN, Pavia ; Bergamo U.)
This work is concerned with the design and characterization of an SLVS transmitter/receiver pair,to be used for I/O links in High Energy Physics applications. Core transistors with a powersupply of 1.2 V have been considered in the design in order to mitigate the TID effects, due tothe harsh radiation environment foreseen [...]
SISSA, 2018 - 5 p. - Published in : PoS TWEPP-17 (2017) 014 Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.014
4.
Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC / Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p. - Published in : PoS TWEPP-17 (2017) 024 Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
5.
Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades / Conti, Elia (CERN) ; Barbero, Marlon (Marseille, CPPM) ; Fougeron, Denis (Marseille, CPPM) ; Godiot, Stephanie (Marseille, CPPM) ; Menouni, Mohsine (Marseille, CPPM) ; Pangaud, Patrick (Marseille, CPPM) ; Rozanov, Alexandre (Marseille, CPPM) ; Breugnon, Patrick (Marseille, CPPM) ; Bomben, Marco (Paris U., VI-VII) ; Calderini, Giovanni (Paris U., VI-VII) et al. /RD53
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. [...]
SISSA, 2017 - 5 p. - Published in : PoS TWEPP-17 (2017) 005 Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.005
6.
65-nm CMOS front-end channel for pixel readout in the HL-LHC radiation environment / Ratti, Lodovico (Pavia U. ; INFN, Pavia) ; Gaioni, Luigi (INFN, Pavia ; Bergamo U.) ; Manghisoni, Massimo (INFN, Pavia ; Bergamo U.) ; Re, Valerio (INFN, Pavia ; Bergamo U.) ; Riceputi, Elisa (INFN, Pavia ; Bergamo U.) ; Traversi, Gianluca (INFN, Pavia ; Bergamo U.)
A charge preamplifier has been developed in a 65-nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High-Luminosity (HL) Large Hadron Collider (LHC). The circuit is part of a readout channel implementing a time-over-threshold method for the analog-to-digital conversion of the input charge signal. [...]
2017 - 11 p. - Published in : IEEE Trans. Nucl. Sci. 64 (2017) 2922-2932
7.
Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC / Ceresa, Davide (CERN) ; Marchioro, Alessandro (CERN) ; Kloukinas, Konstantinos (CERN) ; Jan Kaplon ; Bialas, Wojciech (CERN) ; Re, Valerio (INFN, Pavia) ; Traversi, Gianluca (INFN, Pavia) ; Gaioni, Luigi (INFN, Pavia) ; Ratti, Lodovico (INFN, Pavia)
The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). [...]
CMS-CR-2014-139.- Geneva : CERN, 2014 - 12 p. - Published in : JINST 9 (2014) C11012 Fulltext: PDF;
In : WIT2014 Workshop on Intelligent Trackers, Philadelphia, USA, 14 - 16 May 2014, pp.C110121
8.
Description and performance of track and primary-vertex reconstruction with the CMS tracker / CMS Collaboration
A description is provided of the software algorithms developed for the CMS tracker both for reconstructing charged-particle trajectories in proton-proton interactions and for using the resulting tracks to estimate the positions of the LHC luminous region and individual primary-interaction vertices. Despite the very hostile environment at the LHC, the performance obtained with these algorithms is found to be excellent. [...]
arXiv:1405.6569; CMS-TRK-11-001; CERN-PH-EP-2014-070; CERN-PH-EP-2014-070; CMS-TRK-11-001.- Geneva : CERN, 2014-10-16 - 80 p. - Published in : JINST 9 (2014) P10009 Fulltext: openaccess_2014_J._Inst._9_P10009 - PDF; arXiv:1405.6569 - PDF; cms-trk-11-001-arxiv - PDF; IOP Open Access article: PDF; External links: Fulltext; Open Access fulltext
9.
Alignment of the CMS tracker with LHC and cosmic ray data / CMS Collaboration
The central component of the CMS detector is the largest silicon tracker ever built. The precise alignment of this complex device is a formidable challenge, and only achievable with a significant extension of the technologies routinely used for tracking detectors in the past. [...]
arXiv:1403.2286; CMS-TRK-11-002; CERN-PH-EP-2014-028; CMS-TRK-11-002; CERN-PH-EP-2014-028.- Geneva : CERN, 2014-06-06 - 56 p. - Published in : JINST 9 (2014) P06009 Fulltext: cms-trk-11-002-arxiv - PDF; fermilab-pub-14-075-cms - PDF; arXiv:1403.2286 - PDF; IOP Open Access article: PDF;
10.
Recent progress in the development of 3D deep n-well CMOS MAPS / Traversi, Gianluca (University of Bergamo and INFN) ; Gaioni, Luigi (INFN) ; Manazza, Alessia (University of Pavia and INFN) ; Manghisoni, Massimo (University of Bergamo and INFN) ; Ratti, Lodovico (University of Pavia and INFN) ; Re, Valerio (University of Bergamo and INFN) ; Zucca, Stefano (University of Pavia and INFN)
In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. [...]
AIDA-PUB-2012-001.- Geneva : CERN, 2012 - Published in : JINST 7 (2012) C02007 Fulltext: PDF;

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