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1.
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First test results of the CHIPIX65 asynchronous front-end connected to a 3D sensor
/ Gaioni, L. (Universita di Bergamo) ; De Canio, F. (Universita di Pavia, INFN Pavia) ; Manghisoni, M. (Universita di Bergamo, INFN Pavia) ; Ratti, L. (Universita di Pavia, INFN Pavia) ; Re, V. (Universita di Bergamo, INFN Pavia) ; Sonzogni, M. (Universita di Bergamo, INFN Pavia) ; Traversi, G. (Universita di Bergamo, INFN Pavia)
This work reports on the main results from the experimental characterization of the asynchronous analog front-end integrated in a 65 nm CMOS mixed-signal chip for the readout of high granularity silicon pixel sensors at the high-luminosity upgrades of the
ATLAS and CMS experiments. Such a mixed-signal chip has been designed and submitted in the framework of the CHIPIX65 project, funded by the Italian Institute of Nuclear Physics for the development of an advanced pixel chip in a 65 nm CMOS technology. [...]
AIDA-2020-PUB-2020-010.-
Geneva : CERN, 2019
- Published in : Nucl. Instrum. Methods Phys. Res., A 936 (2019) 319-320
Fulltext: PDF;
In : Frontier Detectors for Frontier Physics: XIV Pisa Meeting on Advanced Detectors, La Biodola, Isola D'elba, Italy, 27 May - 2 Jun 2018, pp.319-320
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2.
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Algorithms for Threshold Dispersion Minimization of the CHIPIX65 Asynchronous Front-End
/ Sonzogni, Mauro ; De Canio, Francesco ; Gaioni, Luigi ; Manghisoni, Massimo ; Re, Valerio ; Traversi, Gianluca ; Ratti, Lodovico
This work discusses four different algorithms for the minimization of threshold dispersion inmultichannel readout circuits for pixel detectors. These algorithms, which are based on differentmethods (e.g. [...]
SISSA, 2019 - 5 p.
- Published in : PoS TWEPP2018 (2019) 076
In : Topical Workshop on Electronics for Particle Physics, Antwerp, Belgique, 17 - 21 Sep 2018, pp.076
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3.
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Experimental Study of Different Silicon Sensor Options for the Upgrade of the CMS Outer Tracker
/ Tracker Group of the CMS Collaboration
During the high-luminosity phase of the LHC (HL-LHC), planned to start around 2027, the accelerator is expected to deliver an instantaneous peak luminosity of up to $7.5\times10^{34}$ cm$^{-2}$s$^{-1}$. A total integrated luminosity of $3000$ or even $4000$~fb$^{-1}$ is foreseen to be delivered to the general purpose detectors ATLAS and CMS over a decade, thereby increasing the discovery potential of the LHC experiments significantly. [...]
arXiv:2001.02023.-
2020-04-22 - 34 p.
- Published in : JINST 15 (2020) P04017
Fulltext: PDF; Fulltext from Publisher: PDF; Fulltext from publisher: PDF;
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4.
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Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications
/ De Canio, Francesco (INFN, Pavia) ; Gaioni, Luigi (INFN, Pavia ; Bergamo U.) ; Manghisoni, Massimo (INFN, Pavia ; Bergamo U.) ; Ratti, Lodovico (INFN, Pavia ; Pavia U.) ; Re, Valerio (INFN, Pavia ; Bergamo U.) ; Traversi, Gianluca (INFN, Pavia ; Bergamo U.)
This work is concerned with the design and characterization of an SLVS transmitter/receiver pair,to be used for I/O links in High Energy Physics applications. Core transistors with a powersupply of 1.2 V have been considered in the design in order to mitigate the TID effects, due tothe harsh radiation environment foreseen [...]
SISSA, 2018 - 5 p.
- Published in : PoS TWEPP-17 (2017) 014
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.014
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5.
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6.
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A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC
/ Pacher, L. (Università di Torino and INFN Sezione di Torino) ; Monteil, E (Università di Torino and INFN Sezione di Torino) ; Paternò, A (Politecnico di Torino and INFN Sezione di Torino) ; Panati, S (Politecnico di Torino and INFN Sezione di Torino) ; Demaria, L (INFN Sezione di Torino) ; Rivetti, A (INFN Sezione di Torino) ; Da Rocha Rolo, M (INFN Sezione di Torino) ; Dellacasa, G (INFN Sezione di Torino) ; Mazza, G (INFN Sezione di Torino) ; Rotondo, F (INFN Sezione di Torino) et al.
The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments.
This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS.
The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. [...]
AIDA-2020-CONF-2018-011.-
Geneva : CERN, 2018
- Published in : PoS Vertex2016 (2017) 054
Fulltext: PDF;
In : VERTEX 2016, La Biodola, Italy, 25 - 30 Sep 2016, pp.054
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7.
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Phase-II Associative Memory ASIC Specifications
/ Stabile, Alberto (Università degli Studi e INFN Milano (IT)) ; Annovi, Alberto (INFN Sezione di Pisa, Universita' e Scuola Normale Superiore, Pisa (IT)) ; Warren, Matthew (University of London (GB)) ; Green, Barry (University of London (GB)) ; Konstantinidis, Nikolaos (University of London (GB)) ; Motuk, Halil Erdem (University of London (GB)) ; Frontini, Luca (Università degli Studi e INFN Milano (IT)) ; Liberali, Valentino (Università degli Studi e INFN Milano (IT)) ; Crescioli, Francesco (Centre National de la Recherche Scientifique (FR)) ; Fedi, Giacomo (Universita & INFN Pisa (IT)) et al.
This documents defines the specifications for the Associative Memory ASIC for Phase-II. [...]
CERN-OPEN-2018-003.
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2018. - 33 p.
Preprint
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8.
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Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, L. (INFN Sezione di Torino, Torino, Italy) ; Monteil, E. (INFN Sezione di Torino, Torino, Italy) ; Demaria, N. (INFN Sezione di Torino, Torino, Italy) ; Rivetti, A. (INFN Sezione di Torino, Torino, Italy) ; Da Rocha Rolo, M. (INFN Sezione di Torino, Torino, Italy) ; Dellacasa, G. (INFN Sezione di Torino, Torino, Italy) ; Mazza, G. (INFN Sezione di Torino, Torino, Italy) ; Rotondo, F. (INFN Sezione di Torino, Torino, Italy) ; Wheadon, R. (INFN Sezione di Torino, Torino, Italy) ; Paternò, A. (Politecnico di Torino and INFN Sezione di Torino, Torino, Italy) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 μm × 50 μm pixel size embedding two different architectures of analog front-ends working in parallel. [...]
AIDA-2020-CONF-2018-004.-
Geneva : CERN, 2018
- Published in : Proceedings of Science
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017
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9.
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Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 024
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
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10.
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Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades
/ Conti, Elia (CERN) ; Barbero, Marlon (Marseille, CPPM) ; Fougeron, Denis (Marseille, CPPM) ; Godiot, Stephanie (Marseille, CPPM) ; Menouni, Mohsine (Marseille, CPPM) ; Pangaud, Patrick (Marseille, CPPM) ; Rozanov, Alexandre (Marseille, CPPM) ; Breugnon, Patrick (Marseille, CPPM) ; Bomben, Marco (Paris U., VI-VII) ; Calderini, Giovanni (Paris U., VI-VII) et al.
/RD53
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 005
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.005
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