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Graphics Processors in HEP Low-Level Trigger Systems / Ammendola, Roberto (INFN, Rome2) ; Biagioni, Andrea (INFN, Rome) ; Chiozzi, Stefano (INFN, Ferrara) ; Cotta Ramusino, Angelo (INFN, Ferrara) ; Cretaro, Paolo (INFN, Rome) ; Lorenzo, Stefano Di (INFN, Pisa ; Pisa U.) ; Fantechi, Riccardo (INFN, Pisa) ; Fiorini, Massimiliano (INFN, Ferrara ; Ferrara U.) ; Frezza, Ottorino (INFN, Rome) ; Lamanna, Gianluca (Frascati) et al.
Usage of Graphics Processing Units (GPUs) in the so called general-purpose computing is emerging as an effective approach in several fields of science, although so far applications have been employing GPUs typically for offline computations. Taking into account the steady performance increase of GPU architectures in terms of computing power and I/O capacity, the real-time applications of these devices can thrive in high-energy physics data acquisition and trigger systems. [...]
2016 - 7 p. - Published in : EPJ Web Conf. 127 (2016) 00011 Fulltext: PDF;
In : Connecting the Dots, Vienna, Austria, 22 - 24 Feb 2016, pp.00011

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A FPGA-based Network Interface Card with GPUDirect enabling realtime GPU computing in HEP experiments / Lonardo, Alessandro (INFN, Rome) ; Ameli, Fabrizio (INFN, Rome) ; Ammendola, Roberto (INFN, Rome2) ; Biagioni, Andrea (INFN, Rome) ; Cotta Ramusino, Angelo (Ferrara U. ; INFN, Ferrara) ; Fiorini, Massimiliano (Ferrara U. ; INFN, Ferrara) ; Frezza, Ottorino (INFN, Rome) ; Lamanna, Gianluca (Frascati ; CERN) ; Lo Cicero, Francesca (INFN, Rome) ; Martinelli, Michele (INFN, Rome) et al.
The capability of processing high bandwidth data streams in real-time is a computational requirement common to many High Energy Physics experiments. Keeping the latency of the data transport tasks under control is essential in order to meet this requirement [...]
2015 - 6 p. - Published in : 10.3204/DESY-PROC-2014-05/16 Fulltext: PDF;

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NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems / Ammendola, Roberto (INFN, Rome2) ; Biagioni, Andrea (INFN, Rome) ; Fantechi, Riccardo (CERN ; INFN, Pisa) ; Frezza, Ottorino (INFN, Rome) ; Lamanna, Gianluca (INFN, Pisa) ; Lo Cicero, Francesca (INFN, Rome) ; Lonardo, Alessandro (INFN, Rome ; Unlisted) ; Paolucci, Pier Stanislao (INFN, Rome) ; Pantaleo, Felice (INFN, Pisa ; Pisa U.) ; Piandani, Roberto (INFN, Pisa) et al.
We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. [...]
arXiv:1311.1010.- 2014 - 7 p. - Published in : J. Phys.: Conf. Ser. 513 (2014) 012018 Fulltext: PDF; External link: Preprint
In : 20th International Conference on Computing in High Energy and Nuclear Physics 2013, Amsterdam, Netherlands, 14 - 18 Oct 2013, pp.012018

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