CERN Accelerating science

Article
Title	Fast CMOS binary front-end for silicon strip detectors at LHC experiments
Author(s)	Kaplon, Jan ; Dabrowski, Wladyslaw
Affiliation	(CERN)
Publication	2004
In:	51st Nuclear Science Symposium and Medical Imaging Conference, Rome, Italy, 16 - 22 Oct 2004, pp.34-38 (v.1)
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC
Abstract	We present the design and the test results of a front-end circuit developed in a 0.25 mu m CMOS technology. The aim of this work is to study the performance of a deep submicron process in applications for fast binary front-end for silicon strip detectors. The channel comprises a fast transimpedance preamplifier working with an active feedback loop, two stages of the amplifier-integrator circuits providing 22 ns peaking time and two-stage differential discriminator. Particular effort has been made to minimize the current and the power consumption of the preamplifier, while keeping the required noise and timing performance. For a detector capacitance of 20 pF noise below 1500 e/sup -/ ENC has been achieved for 300 mu A bias current in the input transistor, which is comparable with levels achieved in the past for a front-end using bipolar input transistor. The total supply current of the front-end is 600 mu A and the power dissipation is 1.5 mW per channel. The offset spread of the comparator is below 3 mV rms.