CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-2003-035
Title	The ATLAS Level-1 Calorimeter Trigger Architecture
Author(s)	Garvey, J (Birmingham U.) ; Hillier, S J (Birmingham U.) ; Mahout, G (Birmingham U.) ; Moye, T H (Birmingham U.) ; Staley, R J (Birmingham U.) ; Watkins, P M (Birmingham U.) ; Watson, A T (Birmingham U.) ; Achenbach, R (Kirchhoff Inst. Phys.) ; Hanke, P (Kirchhoff Inst. Phys.) ; Kluge, E E (Kirchhoff Inst. Phys.) ; Meier, K (Kirchhoff Inst. Phys.) ; Meshkov, P (Kirchhoff Inst. Phys.) ; Nix, O (Kirchhoff Inst. Phys.) ; Penno, K (Kirchhoff Inst. Phys.) ; Schmitt, K (Kirchhoff Inst. Phys.) ; Ay, Cc (Mainz U., Inst. Phys.) ; Bauss, B (Mainz U., Inst. Phys.) ; Dahlhoff, A (Mainz U., Inst. Phys.) ; Jakobs, K (Mainz U., Inst. Phys.) ; Mahboubi, K (Mainz U., Inst. Phys.) ; Schäfer, U (Mainz U., Inst. Phys.) ; Trefzger, T M (Mainz U., Inst. Phys.) ; Eisenhandler, E F (Queen Mary, U. of London) ; Landon, M (Queen Mary, U. of London) ; Moyse, E (Queen Mary, U. of London) ; Thomas, J (Queen Mary, U. of London) ; Apostoglou, P (Rutherford) ; Barnett, B M (Rutherford) ; Brawn, I P (Rutherford) ; Davis, A O (Rutherford) ; Edwards, J (Rutherford) ; Gee, C N P (Rutherford) ; Gillman, A R (Rutherford) ; Perera, V J O (Rutherford) ; Qian, W (Rutherford) ; Bohm, C (Stockholm U.) ; Hellman, S (Stockholm U.) ; Hidvégi, A (Stockholm U.) ; Silverstein, S (Stockholm U.) 39 人のオーサーを表示
Publication	2004
Imprint	31 May 2003
Number of pages	5
In:	IEEE Trans. Nucl. Sci. 51 (2004) 356-360
In:	13th IEEE-NPSS Real Time Conference 2003, Montreal, Canada, 18 - 23 May 2003, pp.356-360
DOI	10.1109/TNS.2004.828800
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	trigger ; calorimeter ; FPGA ; Level-1 ; ATLAS ; pipeline
Abstract	The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/tt cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC Timing, Trigger and Control system (TTC). A common data merger module (CMM) uses FPGAs with multiple configurations for summing electron/photon and tau/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquisition system (DAQ), and region-of-interest (RoI) data to the level-2 triggers. Extensive use of FPGAs throughout the system makes the trigger flexible and upgradeable, and several architectural choices have been made to reduce the number of inter-crate links and make the hardware more robust.
Copyright/License	Preprint: (License: CC-BY-4.0)

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