CERN Accelerating science

LHCb Note
Report number	LHCb-97-024
Title	An alternative architecture of the L0(æ) processor
Author(s)	Aslanides, Elie (Marseille, CPPM ) ; Dinkespiler, B (Marseille, CPPM ) ; Le Gac, R (Marseille, CPPM ) ; Menouni, M (Marseille, CPPM ) ; Potheau, R (Marseille, CPPM )
Submitted by	19 Dec 1997
Subject category	Detectors and Experimental Techniques
Note type	TRIG
Accelerator/Facility, Experiment	CERN LHC ; LHCb
Abstract	97-024 An alternative architecture of the L0(µ) processor and its implementation are presented. The architecture of the processor is based on a strong zero­suppression in order to minimize the data flow coming from the muon detector. It can be achieved by the fast identification of the muon tracks in all muon chambers using adequately dimensioned pad sectors and by transferring the individual pad information only for the regions close to the muon tracks. The proposed solution is simple, flexible and compact. Based on present technology the processor could execute the complete L0(µ) algorithm and make its decision available within less than 3 µs.
Copyright/License	Preprint: (License: CC-BY-4.0)

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