CERN Accelerating science

Article
Title	Design and use of a PPMC processor as shared-memory SCI node
Author(s)	Altmann, D ; Guirao, A ; Müller, H ; Toledo, J
Affiliation	(CERN)
Publication	CERN, 2002
In:	8th Workshop on Electronics for LHC Experiments, pp.392-5
DOI	10.5170/CERN-2002-003.392
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; LHCb
Abstract	The MCU mezzanine was designed as a networked processor-PMC for monitoring and control in the LHCb Readout Unit (RU) with remote boot capability. As PCI monarch on the RU, it configures all PCI devices (FPGAs and readout network interface) that can then be used by user programs running under the LINUX operating system. A new MCU application is within the LHCb L1-Velo trigger where a CPU-farm is interconnected by a 2-dimensional SCI network, with event data input from RU modules at each row of the network: the SCI interface on the RU is hosted by the MCU which exports and imports shareable memory with the trigger farm in order to quasi become part as one of it's CPU. After this initialisation, the hardware DMA engines of the RU can transfer trigger data, by using physical PCI addresses that directly map to the remote CPU memory. (10 refs).