| Article | |
| Title | An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs |
| Author(s) | Firlej, Mirosław (AGH-UST, Cracow) ; Fiutowski, Tomasz (AGH-UST, Cracow) ; Idzik, Marek (AGH-UST, Cracow) ; Kulis, Szymon (CERN) ; Moroń, Jakub (AGH-UST, Cracow) ; Świentek, Krzysztof (AGH-UST, Cracow) |
| Publication | 2023 |
| Number of pages | 16 |
| In: | JINST 18 (2023) P11013 |
| DOI | 10.1088/1748-0221/18/11/P11013 |
| Subject category | Detectors and Experimental Techniques |
| Abstract | The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC.The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW.The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/conv.-step, and is the lowest among the State of the Art designs with similar technology and specifications. |
| Copyright/License | publication: (License: CC-BY-4.0) © 2023-2025 The Author(s) |
Corresponding record in: Inspire
レコード 生成： 2023-12-01, 最終変更： 2024-08-01
