CERN Accelerating science

ATLAS Slides
Report number	ATL-DAQ-SLIDE-2022-543
Title	Global Trigger Versatile Module for ATLAS Phase-II upgrade
Author(s)	Filimonov, Viacheslav (Johannes Gutenberg Universitaet Mainz (DE)) ; Bauss, Bruno (Johannes Gutenberg Universitaet Mainz (DE)) ; Buescher, Volker (Johannes Gutenberg Universitaet Mainz (DE)) ; Schaefer, Uli (Johannes Gutenberg Universitaet Mainz (DE)) ; Ta, Duc Bao (Johannes Gutenberg Universitaet Mainz (DE))
Corporate author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Submitted by	[email protected] on 13 Oct 2022
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	LHC ; ATLAS ; FPGA ; Optical Modules
Abstract	ATLAS detector at the Large Hadron Collider (LHC) will undergo a major Phase-II upgrade for the High Luminosity LHC (HL-LHC). The upgrade affects all the main ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the L0Calo trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module (GCM) as a building block of its design. An additional Global Trigger Versatile Module (GVM) has been designed according to the Global Trigger hardware specifications. To achieve a high input and output bandwidth and substantial processing power, both the GVM and the GCM host the most advanced FPGAs and optical modules, running at high data rates (up to 28 Gb/s) as well as other hardware resources needed for the Global Trigger. The GVM acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the Global Trigger. The GVM is designed in an ATCA form factor with the possibility of a standalone operation. The main building blocks are the following: one large processing FPGA (Xilinx Ultrascale+ VU13P), up to eight Finisar BOA modules for real-time data path, one Finisar BOA module for interface to Front-End Link eXchange (FELIX) system, one UltraZed board with Zynq UltraScale+, one IPM Controller (IPMC), one FPGA power mezzanine and two DDR4 RAMs. In order to optimize the signal integrity for the high-speed signals, dedicated high-speed PCB design techniques, such as physical and spacing constraints, phase tuning, micro and buried vias, were used. Successful results demonstrating a good performance of the on-board components have been obtained. The poster will provide a hardware overview and measurement results of the GVM.