CERN Accelerating science

ATLAS Slides
Report number	ATL-DAQ-SLIDE-2022-511
Title	Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade
Author(s)	Bonini, Filiberto (Brookhaven National Laboratory (US))
Corporate author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Submitted to	Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.ATL-DAQ-SLIDE-2022-511
Submitted by	[email protected] on 30 Sep 2022
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	ATLAS ; Digital electronics ; Global Trigger ; Trigger and Data Acquisition (TDAQ) ; Versal ACAP ; Phase-II
Abstract	The High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs 1-3 combined. Meeting higher throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. In the framework of the ATLAS experiment’s Phase-II Upgrade, new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 $\mu s$-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, called Global Common Module (GCM). GCM is an Advanced Telecommunications Computing Architecture front board. A matching rear-transition module (RTM), called Generic RTM (GRM) was also developed to mitigate the risks deriving from complex design and power management. GRM features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the Front-End Link eXchange (FELIX) subsystem and trigger processors thought optical links, for readout and control. Additionally, GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This summary presents the GRM hardware design and the testing of its key functionalities.