| Hem > CERN Experiments > LHC Experiments > ATLAS > ATLAS Preprints > Fixed-latency gigabit serial links in a Xilinx FPGA for the upgrade of the muon spectrometer at the ATLAS experiment |
| Published Articles | |
| Title | Fixed-latency gigabit serial links in a Xilinx FPGA for the upgrade of the muon spectrometer at the ATLAS experiment |
| Author(s) | Wang, Jinhong (Michigan U.) ; Hu, Xueye (Michigan U.) ; Pinkham, Reid (Michigan U.) ; Hou, Suen (Taiwan, Inst. Phys.) ; Schwarz, Thomas (Michigan U.) ; Zhu, Junjie (Michigan U.) ; Chapman, J W (Michigan U.) ; Zhou, Bing (Michigan U.) |
| Publication | 2018 |
| Number of pages | 9 |
| In: | IEEE Trans. Nucl. Sci. 65 (2018) 656-664 |
| DOI | 10.1109/TNS.2017.2784411 |
| Subject category | Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Abstract | We present an implementation of fixed-latency gigabit serial links in a low-cost Xilinx field-programmable gate array. The implementation is targeted for a data packet router in the upgrade of the ATLAS muon spectrometer. The router serves as a packet switch. It handles up to 12 serial inputs at 4.8 Gbps from on-detector electronics and four 4.8-Gbps outputs to the trigger processing circuits. The input serial streams are deserialized and aligned to a common clock domain for NULL suppression and data packet forwarding. Gigabit transceivers are used in the processing, and a scheme is developed to maintain low and fixed-latency packet multiplexing through the router. We analyze the latency of the scheme and demonstrate its performance in a setup similar to that of the final detector arrangement. |