CERN Accelerating science

Published Articles
Title Latency study of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade
Author(s) Meng, X T (Lanzhou U. (main) ; Michigan U.) ; Levin, D S (Michigan U.) ; Chapman, J W (Michigan U.) ; Li, D C (Lanzhou U. (main)) ; Yao, Z E (Lanzhou U. (main)) ; Zhou, B (Michigan U.)
Publication 2017
Number of pages 18
In: JINST 12 (2017) P02008
DOI 10.1088/1748-0221/12/02/P02008
Subject category Detectors and Experimental Techniques
Accelerator/Facility, Experiment CERN LHC ; ATLAS
Abstract The High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by the CERN Microelectronics group, has been proposed for the digitization of the thin-Resistive Plate Chambers (tRPC) in the ATLAS Muon Spectrometer Phase-1 upgrade project. These chambers, to be staged for higher luminosity LHC operation, will increase trigger acceptance and reduce or eliminate the fake muon trigger rates in the barrel-endcap transition region, corresponding to pseudo-rapidity range 1<|η|<1.3. Low level trigger candidates must be flagged within a maximum latency of 1075 ns, thus imposing stringent signal processing time performance requirements on the readout system in general, and on the digitization electronics in particular. This paper investigates the HPTDC signal latency performance based on a specially designed evaluation board coupled with an external FPGA evaluation board, when operated in triggerless mode, and under hit rate conditions expected in Phase-I. This hardware based study confirms previous simulations and demonstrates that the HPTDC in triggerless operation satisfies the digitization timing requirements in both leading edge and pair modes.

Corresponding record in: Inspire


 Registre creat el 2018-03-23, darrera modificació el 2018-03-24



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