| Article | |
| Report number | arXiv:1702.06713 |
| Title | The ARAGORN front-end—An FPGA based implementation of a Time-to-Digital Converter |
| Related title | The ARAGORN front-end - An FPGA based implementation of a Time-to-Digital Converter |
| Author(s) | Büchele, M. (Freiburg U.) ; Fischer, H. (Freiburg U.) ; Herrmann, F. (Freiburg U.) ; Schaffer, C. (Freiburg U.) |
| Publication | 2017-02-03 |
| Imprint | 2017-02-22 |
| Number of pages | 10 |
| Note | Conference proceeding to the 2016 Topical Workshop on Electronics for Particle Physics |
| In: | JINST 12 (2017) C02006 |
| In: | Topical Workshop on Electronics for Particle Physics, Karlsruhe, Germany, 26 - 30 Sep 2016, pp.C02006 |
| DOI | 10.1088/1748-0221/12/02/C02006 |
| Subject category | hep-ex ; Particle Physics - Experiment ; physics.ins-det ; Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN SPS |
| Abstract | We present the ARAGORN front-end, a cost-optimized, high-density Time-to-Digital Converter platform. Four Xilinx Artix-7 FPGAs implement 384 channels with an average time resolution of 165 ps on a single module. A fifth FPGA acts as data concentrator and generic board master. The front-end features a SFP+ transceiver for data output and an optional multi-channel optical transceiver slot to interconnect with up to seven boards though a star topology. This novel approach makes it possible to read out up to eight boards yielding 3072 input channels via a single optical fiber at a bandwidth of 6.6 Gb/s. |
| Copyright/License | arXiv nonexclusive-distrib. 1.0 |
Corresponding record in: Inspire
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