CERN Accelerating science

Article
Report number	arXiv:1509.06637
Title	FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
Author(s)	Wang, Jinhong (Michigan U.) ; Hu, Xueye (Michigan U.) ; Schwarz, Thomas (Michigan U.) ; Zhu, Junjie (Michigan U.) ; Chapman, J.W. (Michigan U.) ; Dai, Tiesheng (Michigan U.) ; Zhou, Bing (Michigan U.)
Publication	2015
Imprint	20 Sep 2015
Number of pages	8
Note	8 pages, 8 figures, accepted by IEEE - Transactions on Nuclear Science
In:	IEEE Trans. Nucl. Sci. 62 (2015) 2194-2201
DOI	10.1109/TNS.2015.2477089
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Abstract	We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.
Copyright/License	arXiv nonexclusive-distrib. 1.0

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