| Published Articles | |
| Report number | AIDA-PUB-2012-019 |
| Title | The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project |
| Author(s) | Zivkovic, V (NIKHEF) ; Schipper, J.D (NIKHEF) ; Garcia-Sciveres, M (LPNL) ; Mekkaoui, A (LPNL) ; Barbero, M (UBONN) ; Darbo, G (INFN) ; Gnani, D (LPNL) ; Hemperek, T (UBONN) ; Menouni, M (CPPM) ; Fougeron, D (CPPM) ; Gensolen, F (CPPM) ; Jensen, F (LPNL) ; Caminada, L (LPNL) ; Gromov, V (NIKHEF) ; Kluit, R (NIKHEF) ; Fleury, J (LAP) ; Krüger, H (UBONN) ; Backhaus, M (UBONN) ; Fang, X (UBONN) ; Gonella, L (UBONN) ; Rozanove, A (CPPM) ; Arutinov, D (UBONN) |
| Publication | 2012 |
| Imprint | 2012-02-24 |
| In: | JINST 7 (2012) C02050 |
| DOI | 10.1088/1748-0221/7/02/C02050 |
| Subject category | Detectors and Experimental Techniques ; 3: Microelectronics and interconnection technology ; 3.3: Shareable IP Blocks for HEP |
| Abstract | The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed. |
Corresponding record in: Inspire
Email contact: [email protected]
Record created 2015-03-05, last modified 2017-05-24
