Linc Cherix Pa

Chireixs / LINC Power Amplifier for Base Station Applications Using GaN Devices with Load Compensation
by Jijun Bi
TU-Delft Mentors: Dr. ing. L.C.N. de Vreede Jawad Qureshi, Marco Pelk NXP Mentors: John Gajadharsing Mark van der Heijden
Delft University of Technology, September 2008.
A thesis submitted to the Electrical Engineering, Mathematics and Computer Science Department of Delft University of Technology in partial fulfillment of the requirements for the degree of Master of Science.
Approval
Name: Degree: Jijun Bi Master of Science
Title of Thesis: Chireixs / LINC Power Amplifier for Base Station Applications Using GaN Devices with Load Compensation Committee in Charge of Approval: Chair: ____________________
Department of Electrical Engineering

Committee member: ____________________

____________________

____________________

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Abstract
New generations wireless communication systems require linear efficient RF power amplifiers for higher data transmission rates. However, conventional RF power amplifiers are normally designed for peak efficiency under maximum output power condition. Consequently, when the power is backed-off from its maximum point, the amplifier efficiency drops sharply. As a result, the mean amplifier efficiency is much lower than the efficiency at peak power level. The Chireix outphasing power amplifier is one of the most promising techniques that can simultaneously provide high efficiency and high linearity. Such approach was the origin of the term LINC (LInear amplification using Nonlinear Components), a technique that allows the power amplifiers to continuously operate at their peak power efficiency while providing an almost undistorted output signal. In this project, a Chireix outphasing amplifier for 2.14 GHz with load compensation has been fabricated using GaN HEMTs delivered by CREE. A considerable efficiency improvement has been achieved. The simulation result shows that the drain efficiency of 74% is obtained at 49 dBm peak output power, and the efficiency is kept above 55% over 10 dB power back-off range. The drain efficiency of 70% is measured at 48.5 dBm output power. To meet an increasing demand for wireless communication terminals to handle multi-band multi-mode operation, multi-band multi-mode power amplifiers are urgently needed. An investigation into how to implement multi-band Chireixs outphasing amplifiers has been carried out. Two proposals for implementing potential dual-band Chireixs amplifiers have been presented. In addition, a comparison of the efficiency under the condition of static load modulation has been made between GaN HEMT devices and LDMOS devices. The result of the comparison is that GaN HEMT devices conspicuously outperform LDMOS devices in terms of drain efficiency under static load modulation.
Acknowledgements
First, I would like to express my sincere gratitude to my mentor Dr. Leo de Vreede for granting me such a good opportunity to conduct this interesting research and for his guidance and encouragement during the project. Second, I would like to thank the members of HiTeC Group for their assistance, cooperation, and encouragement. Special thanks are given to Mr. Jawad Qureshi for his continuous help throughout the whole project, to Mr. Marco Pelk for providing the input stabilization network, valuable discussions, and timely help in the final phase of my project, and to Mr. W. C. Edmund Neo for helping me in simulations. Next, I would also like to thank NXP Semiconductors for offering me a traineeship opportunity during 2007 and 2008. Finally, My family and my friends have always given me strong support and encouragement in my studies and in other aspects of my life in the Netherlands. Without them, this work would never have been accomplished.
Contents
Chapter 1 Introduction ................................................................................................1 1.1 Project motives and objectives ...............................................................................1 1.2 Thesis structure ........................................................................................................2 Chapter 2 Chireixs outphasing amplifier ..............................................................5 2.1 Outphasing operation ..............................................................................................5 2.1.1 A mathematical description of Chireix's outphasing operation ................6 2.1.2 Theoretical efficiency of Chireix's outphasing amplifier ............................8 2.2 A practical common-mode topology of Chireix's outphasing system ...........15 2.3 A summary of Chireixs outphasing operation .................................................22 Chapter 3 Design of a Chireix's/LINC amplifier ..................................................25 3.1 Design strategies and procedure..........................................................................25 3.2 Amplifier and power combiner choices ..............................................................26 3.3 Power amplifier cell design ..................................................................................27 3.3.1 Device characterization and bias points .....................................................29 3.3.2 Device stabilization ........................................................................................32 3.3.3 Partially compensating the parasitic effects of the package ....................34 3.3.4 Load-pulldetermining the optimum load impedance ..........................35 3.3.5 Functionality verification with ideal components ....................................39 3.3.6 Implementation with realistic components................................................41 3.4 Chireix's outphasing system design ....................................................................44 3.4.1 Power combiner design.................................................................................44 3.4.2 Chireixs outphasing system without load compensation .......................48 3.4.3 Load adjustment for Chireixs/LINC operation .......................................53 3.4.4 Load compensation........................................................................................55 3.4.5 Ideal implementation of Chireixs outphasing system .............................56 3.4.6 Practical implementation of Chireixs outphasing system ......................61 3.5 Layout implementation and measured results ..................................................66 3.6 Summary .................................................................................................................68 Chapter 4 Potential solutions to multi-band Chireix's/LINC amplifier .........69 4.1 A review of several current multi-band PA implementation ..........................69 4.2 Proposals for implementing multi-band Chireixs amplifiers .........................71 4.2.1 Dual-band Chireixs amplifier based on resonators ..................................71 4.2.2 Dual-band Chireixs amplifier based on transmission lines .....................74 4.3 Summary .................................................................................................................76
Chapter 5 Efficiency comparison under static load modulation between GaN HEMT and LDMOS .....................................................................................................77 5.1 Research motivation ..............................................................................................77 5.2 Device models .........................................................................................................78 5.3 Simulation procedures of static load modulation .............................................79 5.4 GaN HEMT 45-watt model ...................................................................................81 5.4.1 Harmonic termination ....................................................................................81 5.4.2 Optimum load .................................................................................................83 5.4.3 Static load modulation ...................................................................................86 5.5 LDMOS 45-watt model ..........................................................................................87 5.5.1 Harmonic termination ....................................................................................87 5.5.2 Optimum load .................................................................................................88 5.5.3 Static load modulation ...................................................................................89 5.6 Comparison and conclusion .................................................................................91 Chapter 6 Conclusions and suggestions .............................................................93 6.1 Conclusions .............................................................................................................93 6.2 Suggestions .............................................................................................................94 References ............................................................................................................................95
Chapter 1. Introduction
Chapter 1 Introduction
1.1 Project motives and objectives
The boom of the wireless market, combined with the intense competition of the past two decades, has stimulated unprecedented interest in the performance of low-cost and physically compact radio frequency (RF) power amplifiers. Interest in performance was induced by the significant impacts that power amplifiers have on wireless communication systems. As far as base station applications are concerned, power amplifiers affect them primarily in two aspects. Firstly, as the final stage in the transmitter chain, the power amplifier (PA) has a significant impact on the total power consumption of the base station. Here low power consumption will result in low operation costs, something that is a substantial market advantage. Consequently, to achieve low operation costs the PA should have high efficiency, not only for the peak-power levels but also for signal with varying envelopes yielding high peak-to-average power ratios. Secondly, PA nonlinearity can cause spectral spreading of the amplified signal, resulting in channel-to-channel interference. To avoid this, the PA must be as linearly as possible.
Figure 1.1: Efficiency and linearity trade-off in RF power amplifiers
Therefore, two specificationsefficiency and linearityneed to be dealt with. Unfortunately, instead of being independent, PA efficiency and linearity are usually
conflicting requirements. For instance, for those systems that employ envelope-varying modulation schemes, a direct trade-off exists between the linearity and efficiency of the power amplifier. E.g. conventional PAs that operate in class-A, class-AB, and class-B can be linear, but are typically inefficient, not only in terms of peak efficiency, but even more in power back-off when amplifying envelope-varying signals. Switch mode PAs like class-D, class-E, and class-F can have high efficiency, but they are usually nonlinear in nature yielding intermodulation distortion (IMD) which results in spectral spreading. Consequently, the main question is how to achieve high efficient amplification with sufficient linearity for envelope varying signals. To tackle this problem up to date (Figure 1.1), several methods have been proposed. An interesting but somewhat neglected concept to solve for the efficiency-linearity trade-off is Chireix's outphasing amplifier, also referred to as "linear amplification using nonlinear components" (LINC). Within NXP progress has already been made with this amplifier concept yielding encouraging results and some patent applications. Meanwhile, a prior M.Sc. study by R. Liu at the TUDelft for application of this amplifier concept in handset PAs has yielded new insights and concepts to further improve the original Chireix's concept. One objective of this project is to combine these existing insights to a new high power amplifier implementation facilitating high efficiency and linearity for base station applications. For this purpose use will be made from state-of-the-art Gallium Nitride (GaN) devices from CREE. In addition, there is an increasing demand for wireless communication terminals to handle multi-band multi-mode operation with a single Power Amplifier. Consequently, to address this need multi-band PAs are needed that do not require extensive filter banks. So the second objective of the project is to review potential implementations of multi-band PAs and to evaluate the feasibility of realizing a multi-band Chireix's outphasing amplifier. As a supplementary topic, the drain efficiencies in class-B mode operation under static load modulation have been investigated for GaN HEMT devices and LDMOS devices. Simulation results show that under static load modulation GaN HEMT devices demonstrate much better drain efficiencies than do LDMOS devices.
1.2
Thesis structure
Chapter 2 describes the concept of Chireix's outphasing amplifier. First, based on a
differential topology, the principle of Chireixs outphasing operation is introduced. Then, for two types of power combiner topologies, the varying load seen by the PA and the ideal drain efficiency are derived. These theoretical results convincingly prove the advantage of
Chireixs outphasing amplifier as an efficiency enhancement technique. Chapter 3 discusses the design procedure of a Chireix's outphasing amplifier in detail. Section 3.1 and 3.2 outline the methodology and strategies that have been adopted in the design of Chireix's outphasing amplifier. Section 3.3 gives details related to the design of the PA cell, including device evaluation, choice of operation class, load-pull simulation, and the realization of the input and output matching network. Section 3.4 describes the design of the overall Chireix's outphasing system. Close attention is paid to the compensation of the parasitic reactance in device package, the realization of the power combiner, and the load adjustment for outphasing operation. A detailed design process has been described by presenting circuit schematic and simulation results in every step from concept verification with ideal devices and components to the real implementation with actual active devices and practical components. Section 4.5 shows the actual layout implementation of the Chireix amplifier and its measured results. A summary of Chapter 3 is given in the last section. Chapter 4 presents the research on potential multi-band amplifiers. This research comprises two parts. The first part is a review of current multi-band PA implementations. In the second part several suggestions on how to implement a multi-band Chireix's outphasing amplifier are proposed. Chapter 5 describes the comparison of the drain efficiency under static load modulation between GaN HEMT devices and LDMOS devices. Chapter 6 concludes the thesis by giving some suggestions on the future work of Chireixs outphasing amplifier.
Chapter 2. Chireixs outphasing amplifier
Chapter 2 Chireixs outphasing amplifier

2.1 Outphasing operation
Outphasing operation is a technique with a long history that was first proposed by Henri Chireix in 1935 to improve average efficiency and linearity of AM broadcast transmitters. This idea has been revived and applied to various wireless applications since it was reinvented by D. C. Cox, who introduced the term LINC (LInear amplification using Nonlinear Components) in 1974. LINC was invented to realize a linear amplifier where the intermediate stages of RF power amplification could employ highly nonlinear devices.
Figure 2.1: Simplified block diagram of an outphasing system
Figure 2.1 illustrates a simplified diagram of an outphasing system. The concept itself is very simple. An amplitude modulated (AM) signal is first separated by the signal component separator (SCS) into two phase modulated (PM) signals that have equal constant envelopes and opposite modulated phase variations. These two constant-envelope PM signals are then amplified separately by two independent identical PAs. Finally, these two amplified signals are combined at the output of the PAs to produce an amplified replica of the original AM signal. The key element in a Chireixs outphasing system is the SCS, which converts the input AM signal into two outphased component PM signals that have constant envelopes. It is exactly such modulation conversion that brings the possibility of highly efficient and highly
linear amplification. Because the envelopes of the signals to be amplified are now fixed and the magnitude of the envelopes contains no information (all the amplitude information of the original AM signal is contained in the phase of the component PM signals), we can employ PA cells in the branches which have an extremely high peak efficiency. Consequently, the Chireixs outphasing amplifier system can act as an interesting efficiency enhancement technique. Meanwhile, also thanks to the fixed envelope in the branch amplifiers, the nonlinearity of the input-output power characteristic as present in most high-efficiency PA implementation will have very little influence on the overall input-output transfer function of the Chireixs outphasing system. As a result, the total system can be highly linear over a wide range of signal levels, provided the SCS and the power combiner do not introduce nonlinear signal distortion. In practice, for the branch amplifiers, the most high-efficiency PAs or even constant-amplitude phase-locked oscillators can be used to realize linear amplification, which explains the acronym LINC that is typically used for these types of amplifiers. In summary, theoretically Chireixs outphasing operation provides a clear, simple, and promising solution for simultaneously achieving high efficiency and high linearity in a power amplifier system. However, as explained later, practical implementation aspects of a Chireixs outphasing amplifier can be complicated.
2.1.1 A mathematical description of Chireix's outphasing operation

The whole process of Chireixs outphasing operation consists of three stepssignal component separation, signal amplification, and signal combination, which are realized respectively by the SCS, the PAs, and the power combiner. The topology of the power combiner has an influence on the signal component separation that should be implemented. The principle of Chireixs outphasing operation will be described for the case of a nonisolating power combiner with a differential topology, as shown in Figure 2.2.
Figure 2.2: A Chireix outphasing system with a differential-topology power combiner
The input AM signal, which may also include phase modulation, is denoted by
Sin (t ) = E (t ) cos[t + (t )]; 0 E (t ) Em
(Equation 2.1)
where E (t ) is the real envelope and (t ) represents the original phase modulation in the input AM signal. This input signal is separated by the SCS into two constant-envelope PM signals having equal envelopes and opposite modulated phase variations
Em sin[t + (t ) + (t )] 2 E S 2 (t ) = m sin[t + (t ) (t )] 2 S1 (t ) =
(Equation 2.2)
where Em is the maximum value of E (t ) and the outphasing angle (t ) produced by the SCS is
(t ) = arcsin[
E (t ) ]; 0 (t ) Em 2
(Equation 2.3)
S1 (t ) and S 2 (t ) are related to Sin (t ) as follows: E S1 (t ) S2 (t ) = m {sin[t + (t ) + (t )] sin[t + (t ) (t )]} 2 = Em sin[ (t )] cos[t + (t )]
= E (t ) cos[t + (t )] = Sin (t )
(Equation 2.4)
S 2 (t )
Sin (t )
(t ) (t )
S 2 (t )
S1 (t )
e j ( t )
Figure 2.3: A complex phasor representation of Chireixs outphasing operation
Figure 2.3 illustrates this relationship expressed by the corresponding complex phasors. 7
The real signals are related to the corresponding complex phasors as follows:
Sin (t ) = Re{Sin (t ) exp( jt )} where Sin (t ) = E (t ) exp[ j (t )] Em exp{ j[ (t ) + (t )]} 2 2 Em exp{ j[ (t ) (t )]} S 2 (t ) = Re{S 2 (t ) exp( jt )} where S 2 (t ) = 2 2 (Equation 2.5) S1 (t ) = Re{S1 (t ) exp( jt )} where S1 (t ) =
These two constant-envelope PM signals are separately amplified by two independent identical PAs. The output signals from the PAs are
Em sin[t + (t ) + (t )] 2 E S `2 (t ) = G S 2 (t ) = G m sin[t + (t ) (t )] 2 S `1 (t ) = G S1 (t ) = G
(Equation 2.6)
where G is the identical amplifier gain. Because of the differential topology of the power combiner, the final output at the load resistor RL is
Sout (t ) = S `1 (t ) S `2 (t ) = G [ S1 (t ) S 2 (t )] = G Sin (t ) = G E (t ) cos[t + (t )] (Equation 2.7)

This final differential signal at the load resistor shows full recovery of the original AM signal. Meanwhile, the original phase modulation (t) in the input AM signal passes through the system unmodified.
2.1.2 Theoretical efficiency of Chireix's outphasing amplifier

As mentioned before, in Chireixs outphasing system, nonlinear PAs can be employed to realize linear amplification. These amplifiers can be so heavily saturated that the device will have rail-to-rail voltage swing. Under these conditions, the device can be approximated as a fixed RF voltage source. In the case of shorted harmonics (class-B), the amplitude of the RF voltage source can be approximated by the dc supply voltage. In this section, the efficiency of Chireixs outphasing amplifier will be derived based on the following assumptions: Heavily saturated class-B amplifiers are used for signal amplification so that the PAs are approximated as ideal voltage sources that have an amplitude equal to dc supply voltage.
Harmonic shorts at the output ensure that the output voltage is a pure fundamental tone
having a sinusoidal form.
A differential-topology lossless power combiner is used for signal combination
Figure 2.4: Simplified output schematic of Chireixs outphasing system
Based on these assumptions, the output of the Chireixs outphasing system can be simplified into a diagram shown in Figure 2.4. The voltages of those two voltage sources can be expressed in the following phasor notation:
V1 = Vo e+ j = Vo (cos + j sin ) V2 = Vo e j = Vo (cos j sin ) with Vo = Vdc and 0

The voltage across the RF load resistor RL is (Equation 2.8)
VL = V1 V2 = 2Vo j sin
(Equation 2.9)
Recall (Equation 2.3 and (Equation 2.5, in the form of voltage signal they become
(t ) = arcsin[
E (t ) ] Em
Vin (t) = V (t )exp{ j (t )}; 0 V (t ) Vm
Vm exp{ j[ (t ) + (t )]} = Vo exp[+ j (t )] 2 2 V V2 (t) = Av m exp{ j[ (t ) (t )]} = Vo exp[ j (t )] 2 2 where Av is the voltage gain of the PAs and
V1 (t) = Av Vo = Av
Vm exp{ j[ (t ) ]} 2 2
(Equation 2.10)
Then the differential output voltage is given by
VL (t) = 2Vo j sin

= 2 Av V (t ) Vm exp{ j[ (t ) ]} exp( j ) 2 2 2 Vm
(Equation 2.11)
= Av V (t ) exp[ j (t )] = Av Vin (t)

which is exactly an amplified recovery of the original input voltage. The impedances seen by each of the voltage sources are
Z1 =
V1 cos + j sin R = RL = L (1 j cot ) V1 V2 2 j sin 2 RL
R V2 cos j sin RL = L (1 + j cot ) = Z* = 1 V V2 2 j sin 2 ( 1 ) RL (Equation 2.12) The corresponding admittances are Z2 =
Y1 = Y2 =
1 2sin 2 sin 2 = +j = Go + jBo Z1 RL RL 1 2sin 2 sin 2 = j = Go jBo = Y1* Z2 RL RL

(Equation 2.13)
2sin 2 sin 2 where Go = and Bo = RL RL

The RF power delivered to the load is
1 1 1 2 PRF 1 = Re{(V1Y1 )* V1} = V1 Re{Y1* } = Vdc 2Go 2 2 2 1 1 1 2 * } = Vdc 2Go = PRF 1 PRF 2 = Re{(V2 Y2 )* V2 } = V2 Re{Y2 2 2 2 2 PRF = PRF 1 + PRF 2 = Vdc Go
(Equation 2.14) For a class-B amplifier, the dc current Idc is related to the fundamental current component I1 as follows:
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I dc =
2 2 2 2 2 2 I1 = I fund = V1Y1 = Vdc Y1 = Vdc Y2 Vdc Y (Equation 2.15)
The total DC power dissipated by the PAs is
4 Pdc = 2 I dcVdc = Vdc 2 Y (Equation 2.16) Consequently, the theoretical efficiency of the Chireixs outphasing amplifier is given by
= PRF Go Go = = = B cos(Y) 4 Y 4 Go2 + Bo2 Pdc is the theoretical efficiency of a class B amplifier 4 (Equation 2.17)
where B =
Therefore, the theoretical efficiency of the Chireixs outphasing amplifier is the efficiency of a class-B amplifier multiplied by the cosine of the phase angle of the load (either admittance or impedance) presented to either voltage source. This conclusion is a direct result from the symmetrical topology of the Chireixs outphasing system that consists of two PA branches, and it does not depend on the topology of the power combiner as long as it is lossless. For the differential-topology power combiner, the final efficiency expressed in the form of the outphasing angle is
= B cos(Y) = B sin
Because
(Equation 2.18)
cos(Y) =
Go G + Bo2
2 o
2sin 2 RL 2sin 2 sin 2 + RL RL

2 2
= sin
(Equation 2.19)
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(a)
(b)
Figure 2.5: Theoretical efficiency of the Chireixs outphasing amplifier (without load compensation); (a) Efficiency versus outphasing angle (b) Efficiency versus normalized output power
Consequently, the efficiency significantly drops as the outphasing angle decreases, which is shown in Figure 2.5. The degradation of the efficiency is caused by the increase impact of the susceptance component on the admittance presented to each PA. To address this problem, Chireix proposed the load compensation method; the basic idea of this method is to compensate the susceptance component by adding a proper shunt reactance.
where Go =
2sin 2 sin 2 and Bo = RL RL
Figure 2.6: Load admittances presented to each outphasing PA; (a) upper branch (b) lower branch
(a)
(b)
Figure 2.7: Normalized conductance and susceptance seen by the PA versus outphasing angle (a) normalized conductance (b) normalized susceptance
According to (Equation 2.13, the admittance presented to each PA consists of a conductive part Go and a susceptive part Bo or -Bo, as illustrated in Figure 2.6. As mentioned 12
before, the culprit for the degradation of the efficiency is the susceptance, which is a function of the outphasing angle. If we add a shunt susceptance with the opposite sign to the existent susceptance at a particular outphasing angle, we can cancel the susceptance and therefore obtain a maximum efficiency at that outphasing angle. Additionally, as a function of the outphasing angle, the susceptance Bo is symmetrical around = 45 (Figure 2.7). Due to this property, if we compensate the susceptance at a particular outphasing angle comp (0<comp <45), which will be referred to as the compensation angle, the susceptance at the outphasing angle (90o-comp) will be also automatically compensated. This load compensation process is shown in Figure 2.8.
Figure 2.8: Load compensation; (a) upper branch (b) lower branch
After the compensating components being added, the new load admittances presented to each PA become
Y1 = Y1 + j ( Bcomp ) = Go + j ( Bo Bcomp ) = = Y2 + j (+ Bcomp ) = Go j ( Bo Bcomp ) = Y2 where Bcomp = sin 2comp RL
sin 2 sin 2comp 2sin 2 + j RL RL sin 2 sin 2comp 2sin 2 j = (Y1)* RL RL
(Equation 2.20) Similar to (Equation 2.17, the efficiency of the Chireixs outphasing amplifier with load compensation is given by
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= B cos(Y ) = B = B
Go Go2 + ( Bo Bcomp ) 2
2
2sin 2
(Equation 2.21)
(2sin 2 ) + (sin 2 sin 2comp )

2
The output RF power remains the same as that in (Equation 2.14 because the added compensating reactance or susceptance is lossless.
Figure 2.9: Normalized efficiency of the Chireixs outphasing system at three compensation angles (comp=10o, 20o, and 45o)
Figure 2.10: Normalized efficiency versus normalized output power at three compensation angles (comp=10o, 20o, and 45o)
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Apparently, a zero compensation angle (comp=0o) corresponds to the case without load compensation ( =B*sin). The normalized theoretical efficiencies for three different compensation angles (comp =10o, 20o, and 45o) of the Chireixs outphasing amplifier are plotted in Figure 2.9. As can be seen from these curves, the choice of compensation angle significantly influences the overall efficiency of the Chireixs outphasing amplifier over the whole outphasing angle range. If the compensation angle is too small, due to the long distance between the two efficiency peaks, the overall efficiency in the higher range of the outphasing angle is very high but the overall efficiency at the lower range of the outphasing angle will be rather low despite one of the efficiency peaks achieved at the compensation angle. If the compensation angle is too large, the efficiency peaks move very close to each other, and except the middle range of the outphasing angle both the efficiency for the lower range and for the higher range of the outphasing angle drop quickly from the peak value, especially in the lower range. Only when we choose a proper compensation angle can we achieve the optimum overall efficiency of the Chireixs outphasing amplifier. Nevertheless, theoretically, a combination of Chireixs outphasing operation and load compensation makes it possible to realize very high efficiency over a wide range of the outphasing angle, which corresponds to a wide range of output power back-off (Figure 2.10). This is exactly the main advantage of the Chireixs outphasing operation as an efficiency enhancement technique.
2.2 A practical common-mode topology of Chireix's outphasing system

The Chireixs outphasing amplifier with a differential-topology power combiner can achieve very high overall efficiency by using proper load compensation. A power combiner with such a topology, however, is less practical since the amplifier loadthe antennawill have a ground connection. Consequently, for practical implementations of the Chireixs outphasing amplifier, a common-mode power combiner realized by quarter-wavelength transmission lines is usually adopted, which is illustrated in Figure 2.11.
Figure 2.11: A practical Chireixs outphasing amplifier with a common-mode power combiner
15
For this topology, we will show that it can perform an equivalent function as that of the differential topology. Except the topology of the power combiner, other assumptions remain the same as those in Section 2.1.2. Under these conditions, we will derive the theoretical efficiency of this Chireixs outphasing amplifier in the following section.
Figure 2.12: Schematic of the output part of the practical Chireixs outphasing amplifier (without load compensation)
Without load compensation, the schematic of the output part of this Chireixs outphasing amplifier is shown in Figure 2.12. First, the load admittance presented to each outphasing PA is obtained by using the transmission matrix of the lossless quarter wavelength line. Then, based on the varying admittance, the theoretical efficiency is derived. The transmission matrix of a lossless transmission line having a characteristic impedance Z0 and an electrical length is
cos A B j sin = C D Z0
transmission matrix is
jZ 0 sin cos
(Equation 2.22)
For a quarter-wavelength line ( =90o) having a characteristic impedance Z0, its
0 A B j = C D Z0 4
branches:
jZ 0 0
(Equation 2.23)
Then we have the input-output relations of the quarter-wavelength lines in the two
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V1 = jZ 0 I o1 and V2 = jZ 0 I o2 I1 = j VL Z0 I2 = j VL Z0
(Equation 2.24)
The voltage sources remain the same as in (Equation 2.8, thus
V1 + V2 Vo (e+ j + e j ) 2Vo cos I L = I o1 + I o2 = = = jZ 0 jZ 0 jZ 0 VL = I L RL = I1 = I 2 = 2Vo cos RL jZ 0
j Z2 2V cos 2V cos = 0 VL = o 2 RL = o where RL Z0 Z0 RL RL (Equation 2.25) Therefore, the load admittances presented to the PAs are 2Vo cos I 2cos 2 sin 2 RL jBo Y1 = 1 = = j = Go + j V1 Vo e RL RL 2Vo cos I 2cos 2 sin 2 RL + jBo = (Y1 )* Y2 = 2 = = +j = Go j V2 Vo e RL RL = where Go 2cos 2 sin 2 = and Bo RL RL
(Equation 2.26) which are illustrated in Figure 2.13.
Figure 2.13: Load admittances presented to each PA in the practical Chireixs outphasing amplifier; (a) upper branch (b) lower branch
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According to (Equation 2.17, the efficiency of this Chireixs outphasing amplifier without load compensation is given by (Equation 2.27. The efficiency as a function of the outphasing angle is plotted in Figure 2.13(a).
= B cos(Y ) = B
Go 2 + Bo 2 Go
= B (
2cos 2 RL 2cos 2 2 sin 2 2 ) +( ) RL RL

(Equation 2.27)
= B cos
Recall (Equation 2.14, the output RF power of the amplifier is given by
= PRF = Vdc 2Go
2Vdc 2 cos 2 RL
(Equation 2.28)
The efficiency versus the normalized output RF power is plotted in Figure 2.13(b). This curve is identical to that in Figure 2.5 but now with an inverse dependence on the outphasing angle, which proves this practical topology is an equivalence of that differential topology discussed in Section 2.1.2.
(a)
(b)
Figure 2.14: Theoretical efficiency of the practical Chireixs outphasing amplifier; (a) Efficiency versus outphasing angle (b) Efficiency versus normalized output power
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Figure 2.15: Load compensation in the practical Chireixs outphasing amplifier; (a) upper branch (b) lower branch
The load compensation in the practical Chireixs outphasing amplifier is shown in Figure 2.15. After the load compensation components being added into the branches, the load admittances presented to each PA in the practical Chireixs outphasing amplifier are
) = Go j ( Bo Bcomp )= Y1 = Y1 + j (+ Bcomp = Y2 + j ( Bcomp ) = Go + j ( Bo Bcomp )= Y2 = where Bcomp sin 2comp RL
sin 2 sin 2comp 2cos 2 j RL RL sin 2 sin 2comp 2cos 2 + j = (Y1)* RL RL
(Equation 2.29) Also according to (Equation 2.17, the theoretical efficiency of the practical Chireixs outphasing amplifier with load compensation is given by
= B cos(Y ) = B = B
Go + ( Bo Bcomp )2 Go
2 2
2cos 2
(Equation 2.30)
(2cos2 ) + (sin 2 sin 2comp )

2
The output RF power remains the same as that in (Equation 2.28 because the added compensating reactance or susceptance is lossless. The normalized efficiency for three different compensation angles (comp =10o, 20o, and 45o) of the Chireixs outphasing amplifier is plotted in Figure 2.16. Note the opposite phase dependency with respect to the earlier found results (Figure 2.9) The normalized efficiency can also be plotted as a function of the
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normalized output RF power, which is illustrated in Figure 2.17.
Figure 2.16: Normalized efficiency versus outphasing angle of the practical Chireixs outphasing amplifier at three compensation angles (comp=10o, 20o, and 45o)
As shown in Figure 2.17, the dependence of the efficiency on the output power back-off is identical to that of the differential topology depicted in Figure 2.10. This is additional evidence that the common-mode topology is the equivalent of the differential topology for the Chireixs outphasing operation. Because of the indispensable ground connection needed by the load antenna, the common-mode topology is chosen for the practical implementation of the Chireixs outphasing amplifier.
Figure 2.17: Normalized efficiency versus normalized output power of the practical Chireixs outphasing amplifier at three compensation angles (comp=10o, 20o, and 45o)
As mentioned before, the topology of the power combiner determines how the SCS should be realized. For a common-mode topology of power combiner, the Chireixs outphasing system needs a different realization of the SCS from that of the differential topology. For the original input signal
20
Vin ( t ) = V (t )exp{ j (t )}; 0 V (t ) Vm

The SCS for the common-mode topology should convert it into two PM signal components in the following forms:
Vm exp{ j[ (t ) + (t )]} 2 V Vin2 ( t ) = m exp{ j[ (t ) (t )]} 2 V (t ) where (t ) = arccos[ ] Vm Vin1 ( t ) =

are:
(Equation 2.31)
Assuming the voltage gain of the PA is Av , the amplified signals at the output of the PAs
Vm exp{ j[ (t ) + (t )]} 2 V V2 (t) = Vo exp[ j (t )] = Av m exp{ j[ (t ) (t )]} 2 V where Vo = Av m exp[ j (t )] 2 According to (Equation 2.25, the output voltage at the load is V1 (t) = Vo exp[+ j (t )] = Av 2 Av
(Equation 2.32)
VL ( t ) =
2Vo cos[(t )] RL = jZ 0
Vm V (t ) exp[ j (t )] 2 Vm RL jZ 0 (Equation 2.33)
= Av
RL Vin ( t ) exp[ j ] Z0 2
Which is a full recovery of the original input signal, except that a phase shift of 90 degrees is introduced which is caused by the quarter-wavelength transmission line. The phasor representation of the Chireixs outphasing operation for the common-mode topology is illustrated in Figure 2.18.
21
Vin1 ( t )
(t )
(t )
Vin2 ( t )
Vin ( t ) e j (t )
Figure 2.18: A complex phasor representation of the Chireixs outphasing operation for the common-mode topology power combiner
2.3
A summary of Chireixs outphasing operation

In this chapter, based on a few assumptions, the principle of the Chireixs outphasing
operation is formulated for the case of a direct differential-topology power combiner as well as for a practical common-mode topology power combiner. Table 2.1 presents a comparison of Chireixs outphasing operation between these two cases. While there are some differences in the expressions, the underlying principle is identical for these two cases. Finally, the normalized theoretical efficiency of the Chireixs outphasing amplifier versus the normalized output RF power at four different outphasing angles0o, 10o, 20o, and 45ois plotted in Figure 2.19, which is applicable to both the differential and common-mode topology. As can be seen from this figure, a proper selection of the load compensation can significantly enhance the efficiency of the Chireixs outphasing amplifier over a considerable range of the output RF power back-off. The next chapter will describe a practical implementation of the Chireixs outphasing amplifier based on the common-mode topology with load compensation.
Figure 2.19: Theoretical efficiency of the Chireixs outphasing system at four different compensation angles (0o, 10o, 20o, and 45o)
22
Table 2.1: A comparison of the Chireixs outphasing operation between a differential topology power combiner and a common-mode topology power combiner Differential topology Input signal Common-mode topology
Vin ( t )
component signals
V (t )exp{ j (t )}; 0 V (t ) Vm Vm exp{ j[ (t ) (t )]} 2 2 V (t ) where (t ) = arcsin[ ] Vm VL = V1 V2 = 2Vo j sin = Av Vin ( t )

= Y1,2 sin 2 sin 2comp 2sin 2 j RL RL
Vin1,2 ( t )
Vm exp{ j[ (t ) (t )]} 2 V (t ) where (t ) = arccos[ ] Vm
Load voltage
VL =
VL ( t )
Load admittances
V1 + V2 2V cos RL = o RL jZ 0 jZ 0 RL Vin ( t ) exp[ j ] Z0 2
= Av
= Y1,2
sin 2 sin 2comp 2cos 2 j RL RL
RF power
PRF = Vdc 2 Re{Y } Vdc 2 2sin 2 RL

2sin 2
PRF
Efficiency
2cos 2 Z2 = 0 where RL RL RL () = B cos(Y ) Vdc 2

2 2
()
(2sin 2 ) + (sin 2 sin 2comp )
2cos 2

2
23
24
Chapter 3. Design of a Chireixs/LINC amplifier
Chapter 3 Design of a Chireix's/LINC amplifier

3.1 Design strategies and procedure
As discussed in Chapter 2, a Chireixs/LINC amplifier consists of three partsthe SCS, the PAs, and the power combiner, and they respectively accomplish signal component separation, signal amplification, and amplified signal component recombination in the Chireixs outphasing operation. Such outphasing amplifier architecture allows for the use of nonlinear PAs driven by constant envelope signals, which can lead to dramatically higher efficiency than linear amplifier operation. These nonlinear PAs exhibit very high efficiency but they dont affect the final distortion levels at the system output because they operate at constant envelope signals. The major factors contributing to the linearity degradation include the SCS, realized either by an analog method or by a digital method, and the path imbalance between the two PA branches. Having an influence both on the efficiency and on the linearity, the power combiner is a place where the efficiency-linearity tradeoff needs to be dealt with. As an AM-PM converter, the SCS is conceptually clear, a practical realization of the SCS, however, is complex and difficult because the generation of the two component signals involves memoryless nonlinear signal processing that requires a high degree of accuracy. Various approaches have been proposed to achieve this function, but difficulties remain in terms of factors, such as implementation complexity, bandwidth, and power consumption, owing to the stringent distortion and noise requirements. A study of this topic alone for a operational hardware implementation needs considerable time and effort. Therefore, instead of striving to realize an analog hardware implemented SCS, we aim for a digital SCS implementation and focused our efforts on the design and implementation of the PAs and the power combiner. For this digital SCS implementation we will rely on arbitrary waveform generators and I/Q (In-phase/Quadrature) up-converting modulators to generate the two phase modulated RF input signals. Software will be used to implement the AM-PM signal conversion. Our final goal is to create an amplifier that provides high efficiency and excellent linearity simultaneously. It seems natural that we carry out the design of the outphasing amplifier in two stepsfirst the design of the efficient PA cells and then that of the power 25
combiner. The first thing in the PA cell design, is to choose a suitable amplifier operation m ode. Depending on the operation mode that is selected, the power combiner design has to be adjusted accordingly because different operations need different output terminations from the power combiner. Consequently, the amplifier mode choice and the power combiner choice must be made together, which should be done before stepping into the PA cell design and the power combiner design.
3.2
Amplifier and power combiner choices

Basically there are two kinds of power combiners: isolating power combiners and non-
isolating lossless power combiners. An isolating power combiner provides isolation between its input ports. In a classical LINC system that employs isolating power combiners, the inherent high linearity of the LINC operation can be preserved, but the considerable power loss in the combiners results in significant efficiency reduction. By contrast, a non-isolating lossless power combiner in the PA output yields significant interaction between the amplifiers, which leads to AM-AM and AM-PM distortion, however it provides a much better efficiency. Therefore, both types of power combiners have advantages and disadvantages when applied in a LINC system. For an outphasing system implemented with an isolating power combiner, the amplifier mode choice is relatively unrestricted because the isolated inputs of the matched combiner provide fixed output terminations at the output of the PAs. For a system using a non-isolating lossless power combiner, however, the output interactions must be carefully designed because the overall output impedance of each component PA is established by the outputs of both PAs. If the PAs act as voltage sources, the overall impedance presented to the amplifier by the power combiner must not be zero for any possible phase difference between the two PAs. In contrast, for the PAs acting as current sources, the overall admittance must not be zero. In a Chireixs outphasing system, as discussed in the previous chapter, the Chireixs power combining technique employs a three-port, non-isolating lossless power combiner implemented by two quarter-wavelength transmission lines. This non-isolating Chireixs combiner introduces significant interaction between the two PAs, which generates timevarying loads that are presented to the output of each PA. The Chireixs outphasing operation requires the two PAs to resemble a behavior that approximates a voltage source. Relevant work has shown that saturated class-B, class-F, and voltage-mode class-D PAs have an output current-voltage relationship that is similar to that of a voltage source. As a result, we
26
can choose either of them to implement a high-performance Chireixs outphasing amplifier. In our design, we chose to implement saturated class-B PAs because the practical achievable efficiency of saturated class-B amplifiers is close to that of class-F amplifiers or voltagemode class-D amplifiers while saturated class-B amplifiers are comparatively easy to realize.
3.3
Power amplifier cell design

The design of a class-B PA cell is to find the conditions under which the given active
device can operate in class-B mode and to realize these conditions also in the circuit. These conditions include bias points, input conditions, output terminations, and stabilization conditions. In order to determine these conditions, first we need to know what is a saturated class-B mode. The power amplifiers are loosely divided into two categories based on how the active device behaves. One is the linear (or transconductance mode) PAs and the other is nonlinear (or switch mode) PAs. Depending on the conduction angle, defined as the part of the RF signal period during which the transistor is carrying current, the linear PAs can be classified into several classes, such as class-A, class-B, class-AB, and class-C. The corresponding output current and voltage waveforms are shown in Figure 3.1. Table 3.1 lists the bias point and conduction angle for each corresponding operation mode.
Figure 3.1: Current and voltage waveforms of PA in different classes of operation
In a class-B mode, the gate bias voltage equals the pinch-off voltage, resulting in a conduction angle of half the RF signal period (), and a halfwave-rectified sinewave for the drain current. Therefore, the transistor consumes less dc power than class-A and is more
27
efficient. With all the harmonics shorted, the output voltage across the load only has a fundamental component and therefore has a perfect sinusoidal waveform. An appropriate choice of the load can make the amplitude of the output voltage equal to the dc supply voltage. Based on these assumptions, the theoretical maximum efficiency of class-B operation is /4 (or 78.5%).
Table 3.1: Classical model of operation
Mode class-A class-AB class-B class-C
Normalized bias point 0.5 0-0.5 0 <0
Normalized quiescent current 0.5 0-0.5 0 0
Conduction angle 2 -2 0-
In a saturated class-B mode, also referred to as an overdriven class-B, the sinewave amplitude of the drain current is increased over the maximum linear swing by raising the input drive level. If the load resistor is assumed to have the ideal linear loadline value that would be designed for optimum class-A operation, a symmetrically clipped voltage waveform will be generated because of the clipping of the current waveform. Such a clipped voltage waveform closely approximates a harmonically synthesized squarewave and therefore brings benefits to efficiency. Both the input condition (the drive level) and the output terminations (including the choice of the load) significantly influence how well a saturated class-B mode can be realized. These conditions can be determined through the load-pull simulation. The squaring of the voltage waveform can effectively enhance the efficiency, in practice, however, due to the transistor knee effect, the clipped waveform will cause a lower peak current swing and, consequently, lower RF power. Therefore, there is a tradeoff between efficiency and power and we have to make a proper compromise when determining the drive level and the load impedance in a load-pull simulation. After knowing what really constitutes a saturated class-B amplifier, we can start designing the saturated class-B PA cell. We follow the following procedures to perform the PA cell design: 1) Check the characteristics of the active device and determine the bias points. 2) Make the device unconditionally stable by introducing a proper input stabilization
28
network. 3) Partially compensate the parasitic effects of the device package. 4) Determine the input conditions and the optimum load impedance by load-pull simulation 5) Use ideal components to verify the functionality of the PA cell. 6) Implement the PA cell by using realistic components.
3.3.1
Device characterization and bias points
Various power amplifier technologies are competing for market share like Si-LDMOS (Lateral-diffused MOS), bipolar transistors, GaAs MESFETs (Metal Epitaxial Semiconductor FET), GaAs (or GaAs/InGaP) HBTs (Hetero-junction Bipolar Transistors), SiC MESFETs, and GaN HEMTs. The properties of GaN HEMT compared to the competing technologies is shown in Table 3.2.
Table 3.2: Attributes of various power amplifier technologies
Attribute Energy Gap (eV) Breakdown E-Field (V/cm) Saturation Velocity (cm/s) Electron Mobility (cm2/Vs) Thermal Conductivity (W/cmK) Maximum Temperature (C) JFOM BFOM
Si 1.11 6.0105 1.0107 1350 1.5 300 1.0 1.0
GaAs 1.43 6.5105 2.0107 6000 0.46 300 3.5 9.6
SiC 3.2 3.5106 2.0107 800 3.5 600 60 3.1
GaN 3.4 3.5106 2.5107 1600 1.7 700 80 24.6
The GaN material has much better BFOM (Baligas figure of merit for power transistor performance) and JFOM (Johnsons figure of merit for power transistors performance) than its competitors. This outstanding performance is attributed to the following advantages it has: 1. The room temperature energy gap of 3.4 eV enables GaN devices to support internal electric fields about five times higher than Si or GaAs, which means GaN has a higher breakdown voltage, a desirable attribute of power devices. 2. As a member of HEMT family, the GaN device also inherits the feature of HEMT high electron mobility. In the RF/Microwave domain, high electron speeds are required to minimize internal device delays. 3. Benefiting from the excellent thermal conductivity of its SiC substrate, the GaN 29
HEMT is very suitable for high power devices with reduced cooling requirements. Therefore, we employ GaN HEMT as the active device in our PA cell design.
(a)
(b)
Figure 3.2: GaN HEMT large signal models; (a) package model CGH40045F (b) bare die model CGH40060D
(a)
(b)
Figure 3.3: The circuit model for package parasitics and the bare die model; (a) package parasitics and bare die model (b) a simplified symbol for both
The active device used in the PA cell is the 45 watt GaN HEMT delivered by Cree. Two sets of large signal models CGH40045F and CGH40060D (Figure 3.2) have been provided for this device. CGH40045F is the large signal model of the whole device package, which models both the die transistor and the package parasitics, whereas CGH40060D is the large signal model for the bare die transistor alone, along with which a circuit model for the package parasitics has also been provided (Figure 3.3). Using the DC simulation in ADS, we can check the DC characteristics of the package model CGH40045F. The ID-VGS and the ID-VDS relationships are plotted respectively in Figure 3.4 and Figure 3.5.
30
Figure 3.4: ID versus VGS (VDS=28V)
Figure 3.5: ID versus VDS (VGS=-3.0V::0.5V::1V)
As can be seen from these figures, the DC characteristics of the GaN device are listed in the following table.
Table 3.3: DC characteristics of Cree GaN HEMT CGH40045F
Device DC characteristics Pinch-off voltage Drain-Source breakdown Transconductance Saturated drain current
Typical Value -2.9V 120V 4000mS 12.5A
Conditions VDS = 28V VGS = -3V~1V VDS = 28V, ID=6A VDS = 28V
For a class-B operation, the gate bias voltage should be set at the pinch-off point. The valid drain voltage for this device is from 28V to 48V. We chose the lowest one as the drain bias voltage so that the device would stay in the saturation during most of the half RF signal period even when the input power backs off. In such a way, the device can better
31
approximate an ideal voltage source. As a result, the bias points for the active device are:
VG = 2.9V and VD = 28V
3.3.2
Device stabilization
Stability is of great importance for an amplifier because all the design goals, such as efficiency and gain, will be lost once oscillation occurs. Therefore, it is essential to check and ensure the stability of the active device before starting the PA cell design. Here we used the single parameter criterion to judge the stability of the device. The criterion is actually an analysis of the small signal S-parameters of the device. For small signal S-parameter simulation, the device should be biased at the linear class-A operation. The schematic used to check the devices stability and the simulation result are shown in Figure 3.6.
(a)
(b)
Figure 3.6: Device stability checking; (a) circuit schematic (b) simulation result
The design frequency for our Chireixs outphasing amplifier is 2.14 GHz. Apparently, this device is not unconditionally stable around the design frequency and it is necessary to make the device stable. Because the load of the outphasing amplifier is modulated by the
32
outphasing angle, the load impedance varies as the envelope of the original AM signal alters. Furthermore, under extreme circumstances the antenna may be even short-circuited or become open-circuit, which may lead to unexpected load impedance presented to the output of the amplifiers. Therefore, to avoid disastrous consequences the safest way to handle the stability problem is making the device unconditionally stable over the whole smith chart by introducing into the circuit a proper stabilization network. Earlier a stabilization network was developed by Mr. Marco Pelk to stabilize the same kind of device in another amplifier design. We also used this stabilization network (Figure 3.7) in our Chireixs outphasing amplifier design. The schematic and simulation result in Figure 3.8 show the stabilization effect of this network.
Figure 3.7: Input stabilization network and its simplified symbol Courtesy of Marco Pelk
(a) 33
(b)
Figure 3.8: Stabilization effect of the stabilization network; (a) circuit schematic (b) simulation result
3.3.3
Partially compensating the parasitic effects of the package
As can be seen from Figure 3.3(a), in the circuit model of the package parasitic effects, there are a -type network and a short transmission line at the drain of the die model. The type network also acts like a very short transmission line. Therefore, the overall effect of the -type network and the short transmission line can be approximated by a parasitic transmission line, which transforms the load impedance presented to it (the fundamental as well as the harmonic ones). Such a parasitic impedance transformer impairs the Chireixs outphasing operation. This impedance transformation effect can be partially compensated by adding a proper transmission line, as shown in Figure 3.9. The principle of this compensation is to make the total electrical length of the added transmission line and the parasitic transmission line roughly equal to or 180 degrees for the fundamental impedance so that the total phase shift of the impedance produced by these two transmission lines is approximately 2 or 360 degrees, i.e. on the Smith chart the impedance is rotated a circle and back to the original point. Ideally, with a complete compensation, the impedance seen by port 1 would be exactly the same as Rin. Note that only a small shift in the real part is remaining after the insertion of the line which realizes a partial compensation. We will include this line in our subsequent load-pull simulations. Because the compensation is carried out for the fundamental impedance, it is only valid for the fundamental impedance, generally not valid for the higher harmonic impedance because the -type network is not a transmission line after all. For a special casethe even harmonic short, especially for the second harmonic short, however, it remains valid enough. The parasitics compensation effect for the second harmonic short can be seen from Marker 2 in Figure 3.9(b). As can be seen from this simulation result, providing even harmonic shorts after the compensating transmission line is approximately equivalent to providing them at the 34
internal drain of the bare die inside the package.
(a)
(b)
Figure 3.9: Partial compensation of the package parasitics (a) circuit schematic (b) simulation results
3.3.4
Load-pulldetermining the optimum load impedance
As discussed before, both the input conditions and the output terminations influence the efficiency. To maximally transfer power from the source to the active device, an input conjugate match is needed. To achieve excellent efficiency, a proper input drive level and optimum fundamental impedance are needed besides suitable harmonic terminations. The input impedance for the input match can be determined by a large signal S35
parameter simulation. Then, based on this input impedance, an input matching network can be implemented. A rough value of the required source power can be estimated by the rated power and gain of the active device. The rated power of the GaN HEMT we use is 45 watts, which means that the maximum output power realizable in practice for this device is 45 watts. Experience from previous work shows that the 45 watt GaN HEMT has a gain about 10 dB. Therefore, a suitable input power level is approximately 4.5 watt or 36.5 dBm. In a load-pull simulation, the fundamental load impedance in a certain region of the Smith chart is swept so that the optimum termination for the maximum efficiency with the maximum practically realizable output power (45W or 46.5dBm) is found. A rough estimate of the optimum real part of the load impedance can be made according to the following loadline equation:
Ropt =
Vdc 28 = = 4.5 I max / 2 12.5/ 2
(Equation 3.1)
which can be used as a starting point of the load-pull simulation. During the whole process of the load-pull simulation, the following steps are carried out: 1) At the input, a 36 dBm power source at 2.14 GHz is provided as the excitation. The source impedance is set at 50 ohm for all the frequency components. At the output, even harmonic shorting is realized by an SCSS (Short-Circuit Shunt Stub); the load impedance is set at 50 ohm for the higher harmonics and the fundamental load impedance is 50 ohm by default before the load-pull simulation 2) A large signal S-parameter simulation is performed to determine the input impedance. The fundamental component of the source impedance is then set at the conjugate of the obtained input impedance to realize an input conjugate match. 3) Perform the load-pull simulation to determine the optimum load impedance under present conditions. 4) Set the fundamental component of the load at the optimum load impedance just obtained. Because of the change of the load, the input impedance also changes, which leads to a slight mismatch at the input. Redo the input match as in step 2 to achieve a new input match. 5) With the new input match, perform the load-pull again to obtain a slightly more accurate value of the optimum load impedance. Because the change of the optimum impedance is
36
slight, it has little influence on the new input match. Consequently, we can accept this input match and obtain a better value of the optimum impedance as well.
(a)
(b)
Figure 3.10: Load-pull simulation; (a) schematic (b) simulation result
The circuit schematic and the simulation results are shown in Figure 3.10. In this schematic, the microstrip line used for package parasitics compensation has been converted into an ideal transmission line (TLcomp) by using the LineCalc in ADS.
Table 3.4: Results of the load-pull simulation and the corresponding conditions
Performance Output Power 46.8 dBm Efficiency PAE 78.4% 71.7%
Input power Source impedance
Conditions 36 dBm 50*(0.031-j*0.127) ohm 0.069-j*0.103 S
Optimum load admittance
37
From the above load-pull simulation, we have determined the input impedance for the input match and the optimum admittance for the maximum efficiency at the maximum output power (Table 3.4). Note that, because power contour and efficiency contour normally have different centers, actually such a load is neither optimum only for the efficiency nor for the output power alone, but is a compromise between high output power and high efficiency. If we choose the load for the maximum output power (48.76 dBm, about 75W), the efficiency will be much lower than 78.5%, the theoretical efficiency of class-B PA. If we choose the load for the maximum efficiency (84.87%), the output power will be much lower than the output power rating of the GaN HEMT (45W or 46.5 dBm). Neither of these two results are desirable for the transmitter in the base station applications. The optimum load we choose is such that the efficiency can be as high as possible while the output power remains slightly above the output power rating, 45 watts. Such a load can be regarded as an optimum one for the maximum efficiency with an output power at the output power rating of the device. In the final Chireix implementation the load will be a varying function of the outphasing angle. However, the data obtained will help us to achieve the peak power conditions for the amplifier to be completed. For this load-pull simulation, one thing needs to explain is the location of the SCSS. As mentioned in Section 3.3.3, the package parasitics compensation is valid enough for even harmonic short, and therefore point B in Figure 3.10(a) is equivalent to the internal drain of the bare die for providing even harmonic short. It is natural that we should put the SCSS at point B to provide nearly perfect even harmonic short for the internal drain. In our load-pull circuit, however, the SCSS was located at point A. The reason is that what the internal drain needs for obtaining maximum efficiency is not a perfect second harmonic short but a second harmonic impedance that is a little bit inductive (a possible explanation for this is that the active device is not an ideal device but a device with inherent parasitics such as parasitic capacitance). It is purely coincident that an SCSS at point A, along with the package parasitics, can provide such a somewhat inductive impedance for the second harmonic. As a result, providing even harmonic shorts at point B or at the internal drain produces rather lower efficiency than at point A. By contrast, the load-pull simulation and results in the case of providing even harmonic shorts at the internal drain are shown in Figure 3.11.
38
(a)
(b)
Figure 3.11: Load-pull simulation with even harmonic shorts at the internal drain; (a) schematic (b) simulation result
In addition, a load-pull simulation aiming for the optimization of the second harmonic short was also performed. With the optimized second harmonic short, the efficiency can be further increased by 2 in percentage, but the price is a drop of the output power. Because the improvement of the efficiency is not significant, we choose not to optimize the second harmonic short. In the following design, we will use the results in Table 3.4 to realize the PA cell.
3.3.5
Functionality verification with ideal components
In this section, the implementation of the class-B PA cell by using ideal components will be described. In order to implement the PA cell, three conditions need to be realized. They are the input match, the even-harmonic shorting, and the output loadline match.
39
(a)
(b)
Figure 3.12: Input matching network realized with ideal transmission lines; (a) circuit schematic (b) simulation result
Figure 3.13: Output matching network realized with ideal transmission lines; (a) circuit schematic (b) simulation result
An input matching network can be realized by using lumped elements or ideal transmission lines to transform the input impedance to the 50 ohm source impedance. The input matching network realized by ideal transmission lines is shown in Figure 3.12. The output matching network can be realized in the same way. Figure 3.13 presents the design of the output matching network. The even-harmonic shorting can be realized by a SCSS. The PA cell realized with ideal components is shown in Figure 3.14. As can be seen from the simulation results, the efficiency and the output RF power are very close to the values obtained from the load-pull simulation.
40
(a)
(b)
Figure 3.14: class-B PA cell realized with ideal components; (a) circuit schematic (b) simulation results
3.3.6
Implementation with realistic components
While simulation with ideal components can show maximum attainable performance, what we really need is a circuit fabricated with realistic components. The input matching network and the output matching network realized with ideal transmission lines can be transformed into practical realizations of microstrip lines by using the LineCalc tool in ADS, so is the SCSS that performs the even harmonic shorting. The input matching network realized with practical microstrip lines and 0603 SMCs (Surface Mounted Components) is illustrated in Figure 3.15 and the output matching network in Figure 3.16 while Figure 3.19 shows the final class-B PA cell realized with realistic components.
(a) (b)
(b)
Figure 3.15: Input matching network realized with SMD capacitor and microstrip lines; (a) circuit schematic (b) simulation result
41
(a)
(b)
Figure 3.16: Output matching network realized with SMD capacitor and microstrip lines; (a) circuit schematic (b) simulation results
SMCs are the components used in Surface Mount Technology (SMT). In SMT, SMCs are mounted directly onto the surface of printed circuit boards (PCBs) to construct electronic circuits. Electronic devices so made are called surface-mount devices or SMDs. In the industry SMT has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. SMCs are usually smaller than their counterparts with leads, such as through-hole components, because they have either smaller leads or no leads at all. They may have short pins or leads of various styles, flat contacts, a matrix of solder balls, or terminations on the body of the component. SMCs are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes. For example, the two-terminal packages of rectangular passive components (mostly resistors and capacitors) are listed in Table 3.5.
Table 3.5: Sizes of two-terminal packages of rectangular passive components (mostly resistors and capacitors)
Type 01005 (0402 metric) 0201 (0603 metric) 0402 (1005 metric) 0603 (1608 metric) 0805 (2012 metric) 1206 (3216 metric) 1806 (4516 metric) 1812 (4532 metric) 2010 (5025 metric) 2512 (6332 metric)
Size 0.016" 0.008" (0.4 mm 0.2 mm) 0.024" 0.012" (0.6 mm 0.3 mm) 0.04" 0.02" (1.0 mm 0.5 mm) 0.063" 0.031" (1.6 mm 0.8 mm) 0.08" 0.05" (2.0 mm 1.25 mm) 0.126" 0.063" (3.2 mm 1.6 mm) 0.177" 0.063" (4.5 mm 1.6 mm) 0.18" 0.12" (4.5 mm 3.2 mm) 0.2" 0.1" (5.0 mm 2.5 mm) 0.25" 0.12" (6.35 mm 3.0 mm)
Typical power rating for resistors 1/32 Watt 1/20 Watt 1/16 Watt 1/16 Watt 1/10 or 1/8 Watt 1/4 Watt 1/2 Watt
In our design, we use 0603 SMD components. The parasitics of the 0603 SMD capacitors are:
42

Series resistance: 0.4 Ohm Series inductance: 0.75 nH
The parasitics of the 0603 SMD resistors are: Series inductance: 0.8 nH
The 0603 SMD pad parasitics are shown in Figure 3.17 and Figure 3.18.
(a)
(b)
Figure 3.17: 0603 SMD two-capacitor component and its simplified symbol; (a) pad parasitics and capacitors (b) simplified symbol
(a)
(b)
Figure 3.18: 0603 SMD three-capacitor component and its simplified symbol; (a) pad parasitics and capacitors (b) simplified symbol
43
(a)
(b)
Figure 3.19: Class-B PA cell realized with realistic components; (a) circuit schematic (b) simulation performance
3.4
Chireix's outphasing system design

Based on high efficiency PA cells, a Chireixs outphasing system can be implemented by
connecting them with an appropriate power combiner. This section describes the procedure of Chireixs outphasing system design. First the design of the Chireixs power combiner is discussed in detail and special consideration for the bandwidth has been given to the design of the power combiner. Then two branches of PA are combined together to constitute a Chireixs outphasing system. The implementation of the Chireixs outphasing system is performed in three steps. First, ideal voltage sources and ideal components are used to verify the concept of Chireixs outphasing operation. Also, ideal voltage sources are replaced by power sources with source impedance to check the influence of the source impedance on the outphasing operation. Next, actual active device and ideal components are used to realize the outphasing system. Finally, all ideal components are replaced by practical components to finish the implementation of a practical Chireixs outphasing system.
3.4.1
Power combiner design
The Chireixs power combining technique employs the three-port, non-isolating lossless power combiner implemented by two quarter-wavelength transmission lines complemented with Chireixs complex load compensation for a particular compensation angle. When the
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outphasing angle is equal to the compensation angle, the efficiency of the total Chireix amplifier should peak. In order to make this efficiency peaking also happen in practice, the impedance offered to the internal device (excluding any parasitics) should be real, this requires that all reactive device elements (e.g. output capacitance) and the susceptance due to outphasing effect must be compensated at these angles.
Gopt
Branch 1
, Z0 4
C DS
compensation
Bopt
RL
Branch 2
Figure 3.20: A simplified circuit schematic for one branch of the Chireixs outphasing system at zero outphasing angle without load compensation
According to the principle of Chireixs outphasing operation discussed in Chapter 3, before compensating the susceptance due to outphasing effect, the efficiency of the outphasing system peaks at zero outphasing angle because the active device is presented with just a real conductance at this outphasing angle. In order to make this peak efficiency equal to the PAs maximum efficiency obtained from the load-pull simulation, the active device should be presented with the optimum admittance (Yopt = Gopt + j*Bopt) determined in the load-pull simulation. This can be realized by making the conductance due to outphasing effect equal to the optimum conductance (Gopt) and compensating the output capacitance with the optimum susceptance (Bopt). The simplified schematic for the circuit at zero outphasing angle without load compensation is shown in Figure 3.20. The characteristic impedance of the quarter wavelength line can be determined by the equal relationship between the conductance due to outphasing effect and the optimum conductance. Such an equal relationship at zero outphasing angle requires:
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G1 | = 0 = Gopt = RL Z0 =
2cos 2 2 i.e. | = 0 = = Gopt RL RL

(Equation 3.2)
2 Z2 = 0 Gopt RL 2 RL = Gopt 2 50 = 38.1 Ohm 0.069
The resulting power combiner is shown in the simplified circuit schematic illustrated in Figure 3.21.
Gopt
Branch 1
, Z 0 = 3 8 .1 O hm 4
C DS
compensation
Bo pt
R L = 5 0 O hm Gopt
, Z 0 = 3 8 .1 O h m 4
C DS
compensation
Bo pt
Branch 2
Figure 3.21: A simplified schematic of the Chireixs outphasing system without load compensation
In this power combiner, the impedance transformation from 50 ohm load to the optimum conductance in each branch is realized by only one stage of matching networkone quarter wavelength line. There are various solutions to such a matching problem. The above solution is the most direct and simplest one, but it is not a wide-band matching network and has a limited bandwidth. Theoretically, wide-band matching networks can be realized by cascading multiple stages (the trajectory of each stage on the Smith chart confined in the lowest Q contour). Too many stages, however, require more components and produce a more complex matching network. Here, we made a compromise between the bandwidth and the simplicity of the matching network. We realized this match by inserting another quarter wavelength line, i.e. by cascading two stages of transmission lines in the matching network. Figure 3.22 presents a simplified schematic of this two-stage power combiner.
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Gopt
Branch 1
, Z0 = 23.5 Ohm 4
C DS
compensation
Bopt
, Z = 30.9 Ohm 4 0
Gopt RL = 50 Ohm
, Z0 = 23.5 Ohm 4
C DS
compensation
Bopt
Branch 2
Figure 3.22: A simplified schematic of the Chireixs outphasing system without load compensation with a two-stage power combiner
(a)
(b)
Figure 3.23 Bandwidth of the single-stage power combiner; (a) circuit schematic (b) simulation result
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For this two-stage power combiner, we have optimized its 3 dB bandwidth by tuning the characteristic impedance of each quarter wavelength line in ADS. Alternatively, we can also make the power transfer of the power combiner a Butterworth type by calculation to obtain an optimum bandwidth. Compared to the simple single-stage realization, the bandwidth has been significantly improved in the two-stage power combiner. Circuit schematic and bandwidth simulation results of the single-stage power combiner and those of the two-stage power combiner are shown respectively in Figure 3.23 and Figure 3.24.
(a)
(b)
Figure 3.24: Bandwidth of the two-stage power combiner; (a) circuit schematic (b) simulation result
3.4.2
Chireixs outphasing system without load compensation
With the power combiner, two branches of PAs can be linked together to construct a Chireixs outphasing system. Before we use the real active device to build the PAs, ideal voltage sources and ideal components are used to verify the functionality of the outphasing
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operation. The circuit schematic and simulation results are shown in Figure 3.25. In order to model the maximum output power of the GaN HEMT (45 watts), the voltage of the ideal voltage source is set at 36.1 volts, which can produce 45 watt output power at the optimum conductance (Gopt = 0.069) in each branch. From the theoretical derivation for Chireixs outphasing operation in Chapter 2, recalling (Equation 2.26, (Equation 2.27, and (Equation 2.28, we have:
Y1,2 = G 2cos 2 sin 2 j = Gopt cos 2 j opt sin 2 2 RL RL
= B cos
PRF =
2Vdc 2 cos 2 = GoptVdc 2 cos 2 RL
The simulation results of the admittance, output power, and the normalized efficiency shown in Figure 3.25(b) agree with these theoretical predictions pretty well. Note that Vdc here represents the amplitude of the ideal voltage source, i.e. 36.1 volts. The reason that it differs from the dc supply voltage (28 volts) is that the PA we have designed is not a perfect class-B mode. For a perfect class-B operation mode, all the higher harmonics should be shorted. In our PA operation, we have only provided even harmonic shorts and left the odd harmonic uncontrolled.
(a) Circuit schematic
(b) Admittance in each branch
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(c) Output power and normalized efficiency

Figure 3.25: Ideal outphasing operation without load compensation; (a) circuit schematic (b), (c) simulation results
Such a Chireixs outphasing system has been realized with the actual active devices and ideal components in the schematic shown in Figure 3.26(a). The simulation results are presented in Figure 3.26 (b) and (c).
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(c) Output power and efficiency

Figure 3.26: Chireixs outphasing system realized with active devices and ideal components (without load compensation); (a) circuit schematic (b), (c) simulation results
These curves do not well correspond to those simulation results of the outphasing operation using ideal voltage sources because the actual active devices are, after all, not ideal voltage sources, although they can be approximated by ideal voltage sources to some extent. One significant difference between an ideal voltage source and the actual class-B PA is that the latter has source impedance. If we replace the ideal voltage sources with power sources that have source impedance, the resulting simulation results will become similar to the results of the outphasing system using actual active devices. The outphasing system constructed by using power sources and ideal components is shown in Figure 3.27(a), and the simulation results are presented in Figure 3.27 (b) and (c).
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(c) Output power and normalized efficiency

Figure 3.27: Ideal outphasing operation without load compensation (using power sources that have source impedance); (a) circuit schematic (b), (c) simulation results
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Note that the source impedance has been set equal to the inverse of the optimum conductance so that the maximum output power can be obtained for the optimum load. Power sources with source impedance can approximate the actual active device more accurately, but they are still simplified models of the actual active devices. Consequently, although very similar to the curves of the outphasing system using actual active devices, the simulation results still differ from them.
3.4.3
Load adjustment for Chireixs/LINC operation
For a PA cell realized with one active device, if the reactive device elements (e.g. output capacitance) could be fully compensated, the optimum load for the maximum output power at a proper level of high efficiency would be the resistance obtained from the loadline match condition:
Ropt =
Vdc I max / 2
(Equation 3.3)
Furthermore, even if the load resistance deviates from the loadline match value (e.g. becoming larger than Ropt), although the output power will deviate from the maximum value, the efficiency can still remain at a level comparable to the efficiency obtained at the optimum resistance as long as the load resistance is far smaller than the output resistance of the active device. On the other hand, if the output capacitance is not fully compensated by the reactive load, the efficiency will degrade as the load resistance deviates from the optimum resistance.
In a Chireixs outphasing system, a varying load produced by the outphasing operation is presented to the PA in each branch. Both the load conductance and the load susceptance are modulated by the outphasing angle. With the load compensation, the load susceptance due to outphasing effect is compensated at two compensation angles (comp and 90o-comp). With a proper susceptance Bpro added to completely compensate the output capacitance (CDS) of the active device, the efficiency should peak and become close to the efficiency obtained at the optimum conductance at these two compensation angles. High efficiency at two compensation angles is key to the good performance of a Chireixs outphasing system. A proper load admittance, especially a proper load susceptance Bpro, is needed to ensure the achievement of high efficiency at these compensation angles. In Section 3.3.4, we have obtained the optimum load (Yopt = Gopt + j*Bopt) from the load-
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pull simulation. There is no guarantee that the susceptance Bopt chosen from the load-pull simulation can fully compensate the output capacitance of the active device because the loadpull simulation is carried out only at zero outphasing angle. In the outphasing operation, such a load only ensures that the maximum efficiency with the maximum output power is obtained at zero outphasing angle when without load compensation. It does not guarantee the same high efficiency at two compensation angles. In order to make sure that high efficiency can be achieved at two compensation angles, a proper susceptance Bpro has to be found which can better compensate the output capacitance of the active device. To do this, the circuit schematic in Figure 3.28 is used.
(a)
(b) Bopt=-0.103
(c) Bopt=-0.087
Figure 3.28: Optimum load adjustment for Chireixs outphasing operation; (a) circuit schematic (b), (c) simulation results before and after load adjustment
In this circuit, an admittance equation component is used to model the conductance generated by the upper branch of the power combiner at the compensation angle. The conductance as a function of the outphasing angle is described as:
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G () = Gopt cos 2 ( )
(Equation 3.4)
In our design, we aim to compensate the susceptance due to outphasing operation at 20 and 70 degree. Therefore, the optimum load susceptance need to be adjusted so that high efficiency can be achieved at these two compensation angles. Before the load adjustment, the load used in the outphasing operation is the optimum load obtained from the load-pull simulation. As can be seen from the simulation result in Figure 3.28(b), the efficiency at 20 degree is close to the efficiency at zero outphasing angle, but the efficiency at 70 degree is much lower. An outphasing system based on such a load will not have good performance. The reason is that the optimum susceptance Bopt is not good enough for fully compensating the output capacitance of the active device. The load susceptance need to be adjusted. After the adjustment of the load susceptance, the simulation result is shown in Figure 3.28(c). Both the efficiency at 20 degree and that at 70 degree outphasing angle are very high, comparable to the efficiency obtained from the load-pull simulation. As a result, the new optimum load is:
Gopt = 0.069 Bopt = 0.087
(Equation 3.5)
The Chireixs outphasing system will be based on this new optimum load admittance.
3.4.4
Load compensation
For load compensation, the compensating susceptance is:
Bcomp =
sin(2comp ) sin(2comp ) sin(2comp ) = = Gopt RL 2 / Gopt 2
(Equation 3.6)
In order to compensate the output capacitance of the active device, optimum susceptance components are needed by two branches. The combination of optimum susceptance and the compensating susceptance gives:
B1 = Bopt + Gopt B2 = Bopt Gopt
sin(2comp ) 2 sin(2comp )
(Equation 3.7)
2 These susceptance components can be realized by shunt stubs. After adding the compensating susceptance components, the Chireixs outphasing system is illustrated by the simplified schematic in Figure 3.29.
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B ranch A
,Z 0 4
C DS
compensation
Bopt
B co m p
lo ad c ompe ns a tion
, Z1 4
B ranch B
R L = 5 0 O hm
,Z 0 4
C DS
compensation
Bopt
B c om p
loa d co mp en s atio n
Figure 3.29: A simplified schematic of the Chireixs outphasing system with load compensation
3.4.5
Ideal implementation of Chireixs outphasing system
For this ideal implementation of Chireixs outphasing system, we also perform the design in three steps. First, we use ideal voltage sources and ideal components to verify the concept of load compensation. Next, ideal voltage sources are replaced by power sources that have source impedances to see the change of the simulation results. Finally, we use the actual active device, along with other ideal components, to check the functionality of the Chireixs outphasing system. The circuit used to verify the concept of load compensation and the simulation results are shown below.
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(b) Simulation results

Figure 3.30: Concept verification of Chireixs outphasing system with load compensation by using ideal voltage sources and ideal components; (a) circuit schematic (b) simulation results
Recalling the theoretical derivation for the load compensation, i.e. (Equation 2.29, (Equation 2.30,
= Y1,2 sin 2 sin 2comp G 2cos 2 j = Gopt cos 2 j opt (sin 2 sin 2comp ) RL RL 2
= B cos(Y ) = B
2cos 2

2
we can see the simulation results of the varying admittance and the efficiency correspond to the theoretical results very well. Comparing the simulated efficiency curves with those in Figure 2.16 and Figure 2.17, we can draw the same conclusion.
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With the ideal voltage sources replaced by power sources having source impedance, the circuit schematic and simulation results become:
(b) Simulation results

Figure 3.31: Ideal Chireixs outphasing system with load compensation (realized by using power sources having source impedance and ideal components); (a) circuit schematic (b) simulation results
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One remarkable effect of the source impedance in the power sources is that the conductance now peaks at about 10 degree, between zero outphasing angle and the compensation angle (20 degree), instead of peaking at zero outphasing angle. Due to the change of the conductance curve, the output power now also peaks between zero outphasing angle and the compensation angle because theoretically the output power is proportional to the conductance ((Equation 2.28). The reason is that with load compensation, both the conductance at zero outphasing angle and the conductance at 20 degree (i.e. the compensation angle) considerably deviate from the optimum conductance for the maximum output power (i.e. Gopt). At a particular point between these two angles, however, a load close to the optimum load appears which has conductance very close to Gopt, and therefore the output power peaks at that point. Finally, we use actual active devices and the ideal component to realize a Chireixs outphasing system with load compensation. The circuit schematic is shown in Figure 3.32 and Figure 3.33 presents the simulation results. As can be seen from the simulation results, the varying susceptance due to outphasing effect has been compensated at 20 degree and 70 degree outphasing angles. At these two compensation angles, both the output power and the efficiency for the two branches become equal because the loads for two branches become identical. Because very high efficiency (over 80%) has been realized at these two compensation angles, the overall efficiency of the Chireixs system remains high over a wide range of output power back-off.
Figure 3.32: Chireixs outphasing system realized with actual active devices and ideal components
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(a) Varying load seen by Bopt
(b) Varying load including Bopt
(c) Varying load seen at the internal drain of each GaN HEMT
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(d) Efficiency and output power (thin for branch, thick for total)
(e) Efficiency, output power, and efficiency versus output power

Figure 3.33: Simulation results of the ideal implementation of the Chireixs outphasing system
3.4.6
Practical implementation of Chireixs outphasing system
Based on the ideal realization of the Chireixs outphasing system, a practical outphasing system can be implemented by using practical components. First, all ideal transmission lines should be replaced by practical microstrip lines. Based on the substrate used, the equivalent microstrip line dimensions of a particular ideal transmission line can be calculated by using LineCalc in the ADS. At the crossings of transmission lines, microstrip bends or junctions have to be added to ensure the continuity of the transmission. After microstrip junctions are added, the dimensions of the microstrip lines connected to the junctions need to be adjusted 61
to compensate the effect of the junction. While the process of replacing ideal transmission lines with microstrip lines seems clear, it is not always easy to transform an ideal transmission line network into a practical microstrip line network that fulfills an identical function. Usually the adjustment of the dimensions of the microstrip lines, i.e. the tuning of the size, is time-consuming because several parameters that correlate with each other might need to be tuned at the same time. Second, all the dc block components should be substituted by practical SMC capacitors and dc feed components should be replaced by practical bias inductors. Finally, additional microstrip lines are used at abrupt junctions (TL7 and TL8) or at the biasing (TL21 and TL22) in order to make signal transmission more continuous. The final practical implementation of this Chireixs outphasing amplifier is shown in Figure 3.34. Figure 3.35 shows the simulated performance of this outphasing system. The efficiency is about 74% at the peak output power and is kept above 55% over 10 dBm output power backoff range.
(a) A panoramic view of the whole circuit
(b) Input part and output part of the upper branch

Figure 3.34: Circuit schematic of the practical Chireixs outphasing amplifier; (a) schematic of the whole circuit (b) input part and output part of one branch
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(a) Admittance seen before the output matching network
(b) Admittance seen at the internal drain of GaN HEMT
(c) Output power and efficiency (thick for total, thin for branch values calculated at the reference point of Yline)
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(d) Efficiency versus output power

Figure 3.35: Simulated performance of the Chireixs outphasing amplifier
As can be seen from the efficiency curves in Figure 3.35(c), the total efficiency is not equal to the average of the two branch efficiencies, which means there are some losses in the circuit. In addition, it has also been noted that the loss at a large outphasing angle (e.g. 70 degree) is much higher than that at a small outphasing angle (e.g. 20 degree). In order to check the distribution of the losses, several current probes and voltage labels are added at different locations to calculate the different output power at the compensation angle. The circuit schematic used is shown in Figure 3.36(a) and the simulation results are shown in Figure 3.36 (b) and (c). Figure 3.36(b) shows that the main losses are located at the components before and after the reference point of Vload1, i.e. the microstrip line used for package parasitics compensation and the load compensation network. Another loss contributor is the microstrip curve bend used in the power combiner, which also causes a considerable amount of loss. The distribution of the losses in another branch has been found similar. These microstrip line networks are constituted not by ideal transmission lines but by practical microstrip lines based on a particular substrate, and therefore they cause some losses. In order to investigate the reason why the loss at large outphasing angle is higher than that at small outphasing angle, the loss as a function of the outphasing angle has been plotted in Figure 3.36(c). As can be seen from this curve, the loss goes up as the outphasing angle
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increases.
(a)
(b) Output power at 20 degree
(c) Main loss versus outphasing angle

Figure 3.36: Checking the losses in the Chireixs outphasing system; (a) circuit schematic (b) output power at 20 degree (c) main loss versus outphasing angle
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The reason can be found by examining the curve of the varying conductance generated by the power combiner. As the outphasing angle increases, the conductance, modulated by the outphasing angle, gradually decreases. At 20 degree, the conductance is very close to the optimum conductance needed for the maximum output power. At 70 degree, however, the conductance becomes far smaller than the optimum value. In other words, the varying load at 20 degree is close to the power match for the maximum output power and therefore little power is reflected by the load compensation network; by contrast, at 70 degree, the load considerably deviates from the power match and, as a result, more power is reflected by the load compensation network. Such reflected power will travel back as a power wave, and will be reflected again when it reaches the drain biasing network at the T-junction Tee1. Consequently, the power wave will experience multiple reflections between two T-junction Tee1 and Tee2. Every time the power wave goes through the microstrip line used for package parasitics compensation (i.e. TL4) or the load compensation network, some of its power will be dissipated and at a certain time all the power will be exhausted. The power dissipated is loss. At the very beginning, the load compensation network reflects more power at 70 degree than at 20 degree. As a result, the loss at 70 degree is higher than at 20 degree. This is also the reason why the theoretically supposed second peak of the total efficiency curve does not appear around 70 degree.
3.5
Layout implementation and measured results
Figure 3.37: Layout of the Chireixs outphasing amplifier
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Figure 3.37 presents the final layout of this Chireixs outphasing amplifier, which was designed by using ADS Momentum. A prototype of this outphasing amplifier was fabricated and its performance measured (with the help of Mr. Jawad Qureshi). Figure 3.38 is a block diagram of the test bench for measuring the performance of this Chireixs outphasing amplifier. As mentioned before, instead of using an analog SCS, we rely on arbitrary waveform generator, along with the I/Q (In-phase/Quadrature) up-converting modulators, to generate two outphased PM input signals (RFin1 and RFin2) for the Chireixs outphasing amplifier. Before these two PM signals enter the outphasing amplifier, each of them is first preamplified by two preamplifiers. The RF output signal of the outphasing amplifier is first attenuated and then sent to a mixer to be down-converted so that the original informationcarrying signal can be recovered. The data of the recovered signal is first acquired by using data acquisition cards (with a data rate of 100 mega samples per second) and then is sent to the system PC with MATLAB to be compared with the original signal generated by the arbitrary waveform generator. A spectrum analyzer is used to analyze the spectrum of the attenuated RF output signal.
Mixer
Arbitrary Waveform Generator
MATLAB
Data Acquisition Cards 100 MS/sec
LO
RF
IF I1 LO Q1 RFin1 Pre-amp Pre-amp RFout 2.12MHz
I/Q Modulator 1
Attenuation
I2 LO
Q2 RFin2 Pre-amp Pre-amp Chireixs Outphasing Amplifier Spectrum Analyzer
I/Q Modulator 2
Power Divider
LO Synthesizer
Figure 3.38: Test bench of the Chireixs outphasing amplifier
Figure 3.39 shows the measured efficiency as a function of the output power for different outphasing angles. As the outphasing angle increases, the conductance presented to each active device will gradually decrease. If the input power is fixed at the level for the maximum output power, which means the device is still overdriven, due to the decrease of the load conductance, the output power at high outphasing angle drops significantly, whereas the dc 67
power remains comparatively high because the device is still overdriven. As a result, the efficiency at high outphasing angle becomes very low. If the input power is backed off, better efficiency can be achieved for the dc power will also start to go down. In the measurement, in order to find the best efficiency achievable for a certain outphasing angle, the output power of the amplifier is backed off by decreasing the input power. For an outphasing angle near the compensation angle, the efficiency of about 70% was measured at 48.5 dBm output power. This is the best measurement result of the Chireixs outphasing amplifier we have designed.
Figure 3.39: Measured efficiency versus output power for different outphasing angles
3.6
Summary
Based on the principle of Chireixs outphasing operation, a Chireixs outphasing
amplifier with load compensation was implemented by using GaN HEMT and transmission lines. The circuit design and the layout design was carried out by using ADS 2005A. Simulation results show that the drain efficiency of 74% is obtained at 49 dBm output power and the efficiency is kept above 55% over 10 dB output power back-off range. A prototype based on microstrip lines was fabricated and the drain efficiency of 70% was measured at 48.5 dBm output power.
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Chapter 4. Potential solutions to multi-band Chireixs/LINC amplifier
Chapter 4 Potential solutions to multi-band Chireix's/LINC amplifier

4.1 A review of several current multi-band PA implementation
To meet an increasing demand of modern wireless communication terminals to handle different standards with a single power amplifier, multi-band multi-mode PAs are urgently needed. To date, several methods for achieving multiple band coverage in the transmitter have been proposed in literature. Basically, present multi-band PA implementations can be divided into several typesmulti-band PAs based on switches, those based on diplexers, and those based on electronically tunable elements. Figure 4.1 presents the block diagram of a 2.4 GHz/5.2 GHz CMOS PA for dual-band applications. This dual-band selection is realized by using a NMOS SPDT (Single Pole Double Throw) band switch. At 2.4 GHz and 5.2 GHz bands, the achieved saturated output power are 9.7 dBm and 19.5 dBm, respectively. The PAE (Power Added Efficiency) at 5.2 GHz is 15.3%.
Figure 4.1: Block diagram of a dual-band PA based on band switch (Courtesy of E. Yun Seong and L. Kwang Du)
Figure 4.2 illustrates an 800/1500 MHz 1 watt-class GaAs FET amplifier. In this implementation, the band selection is realized by using the two-frequency lumped-element
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matching circuits which is designed based on the low-pass Chebyshev-form impedance transformer design method. This dual-band PA exhibits the saturated output powers of 30.9 dBm and 28.2 dBm with the PAE of 51.6% and 51.9% at 800 MHz and 1500 MHz, respectively.
Figure 4.2: Configuration of a dual-band PA (Courtesy of K. Uchita et al.)
Figure 4.3 shows a 2.4/5 GHz dual-band PA module realized by using diplexer-matching. This dual-band PA exhibits an output power 20 dBm at 2.4 GHz and 18 dBm at 5 GHz with an EVM (Error Vector Magnitude) of 4-5% for a 54-Mbps OFDM (Orthogonal FrequencyDivision Multiplexing) signal.
Figure 4.3: Block diagram of a 2.4/5 GHz diplexer-matching PA module (Courtesy of K. Kunihiro et al.)
In these multi-band PA implementations, various band selection approaches are employed such as switches, diplexers, and resonators. Each of these approaches has some disadvantages. E.g. for multi-band PAs based on switches or diplexers, the drawbacks caused by the additional band selection circuits are apparentthe PA being less compact and high cost. Moreover, many of these solutions to multi-band applications are unable to provide concurrent operation because of the fact that a change in transmitting frequency requires adjustment of tunable components, change of connection to different matching network, or even between different modules. In order to solve these problems, new approaches for
70
implementing multi-band PAs are needed.
4.2
Proposals for implementing multi-band Chireixs amplifiers

The key to implementation of multi-band Chireixs outphasing amplifiers is finding a
suitable band selection approach that can be employed in Chireixs outphasing operation. For this purpose, here we propose two approaches for implementing dual-band Chireixs outphasing amplifiers. Idealized voltage sources (to model active devices) and idealized components are used to realize an idealized Chireixs outphasing operation to test the feasibility of these two approaches for dual-band application.
4.2.1 Dual-band Chireixs amplifier based on resonators

The first idea for realizing dual band selection is based on the use of resonators. The circuit schematic used to check the feasibility of this approach is shown in Figure 4.4. These resonators, which are composed of ideal capacitors and inductors, are used to realize shorts and open circuits for the dual bands 2.14/4.28 GHz. Load compensation components of the Chireixs outphasing operation are realized by ideal admittance equations.
Figure 4.4: A dual-band Chireixs amplifier model based on resonators
Because the active devices are modeled by ideal voltage sources, according to (Equation 2.30, the efficiency of this idealized Chireixs outphasing system equals the cosine of the
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phase of the varying admittance seen by each device. Because admittance is the ratio of current to voltage, the phase of the admittance is equal to the phase difference between current and voltage. Therefore, alternatively, the efficiency can also be calculated by the following method. First, the in-phase input power of each branch is calculated which does not include the phase relationship between current and voltage.
P 1 = 0.5 I1 V1 P2 = 0.5 I 2 V2
voltage phase difference.
* Pout = 0.5 real { I o Vo }
(Equation 4.1)
Then, the normal output power of the system is calculated which includes the current-
(Equation 4.2)
The ratio of the sum of these two input in-phase power to the output power is then equal to the efficiency of the idealized Chireixs outphasing system.
Pout P 1+P 2
(Equation 4.3)
If the transmission efficiency of the power combiner is pc, which is defined as the ratio of the output power of the power combiner to the sum of the input powers at each branch of the power combiner, then the output power can be expressed by
* Pout = ( Prf 1 + Prf 2 ) pc = (0.5 real { I1*V1 } + 0.5 real { I 2 V2 }) pc
= 0.5 I1 V1 cos( ) + 0.5 I 2 V2 cos( ) pc = (0.5 I1 V1 + 0.5 I 2 V2 ) cos( ) pc = (P 1+P 2 ) cos( ) pc
(Equation 4.4)
Where is the phase difference between current and voltage at any branch. Then, the efficiency can be expressed by
Pout = cos( ) pc P P + 1 2
(Equation 4.5)
In our idealized dual-band Chireixs outphasing amplifier, all components of the power combiner are idealized and therefore there is no loss in the power combiner. As a result, the 72
transmission efficiency of the power combiner is unity. Apparently, this total efficiency is equivalent to the cosine of the phase difference between current and voltage, i.e. the cosine of the phase of the admittance. However, if there is some loss in the circuit, the above efficiency also includes the transmission efficiency of the power combiner. This definition of efficiency is more accurate, and therefore is used in the simulation of the dual-band Chireixs outphasing amplifier. The simulation results are shown in Figure 4.5.
(a) fundamental frequency
(b) double frequency

Figure 4.5: Simulation results of the dual-band Chireixs outphasing amplifier based on resonators; (a) at the fundamental frequency (b) at double frequency
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The simulated efficiency curves agree with the theoretical results derived in Chapter 2 very well, which shows that the designed resonators have realized good isolation and connection at corresponding frequencies so that this Chireixs outphasing amplifier functions well both at the fundamental frequency and at the double frequency. In the simulation results, current and voltage values have been provided to show the functioning of these resonators.
4.2.2 Dual-band Chireixs amplifier based on transmission lines

The second idea for realizing dual band selection is based on the use of special transmission lines such as /4 lines and /8 lines. The circuit schematic used to check the feasibility of this approach is shown in Figure 4.6.
(b) Isolation and connection network realized by special transmission lines
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(c) simulation results at the fundamental frequency
(d) Simulation results at the double frequency

Figure 4.6: A dual-band Chireixs outphasing amplifier model based on special transmission lines (a), (b) circuit schematic (c), (d) simulation results
The calculation of the efficiency has followed the same definition as that in Section 4.2.1. These simulated output power curves and efficiency curves show that this dual-band Chireixs outphasing amplifier functions well both at the fundamental frequency and at the double frequency. This dual-band realization based on special transmission lines has an advantage over the one based on resonators. Provided that the active devices that can operate
75
at both bands are available, this dual-band Chireixs outphasing amplifier is able to concurrently operate at the dual bands, saving the need of band-switches.
4.3
Summary
Several present multi-band PA implementations have been reviewed so that some
inspiration can be obtained for implementing multi-band Chireixs outphasing amplifiers. Two ideas for how to realize dual-band Chireixs amplifier have been proposed. One realization of dual-band Chireixs outphasing amplifier is based on resonators. This dualband realization still needs some kind of band-switch to realize band-selection. Another dualband Chireixs outphasing amplifier is based on using special transmission lines. The advantage of the second realization is that it can concurrently operate at the dual bands without using additional band-selection components, provided the active devices that can simultaneously operate at dual bands are available. Circuit schematic and simulation results of both dual-band realizations have been provided to show their functionality.
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Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and LDMOS
Chapter 5 Efficiency comparison under static load modulation between GaN HEMT and LDMOS
5.1 Research motivation
For an active device in (linear) class-B operation mode, the best efficiency at the maximum output power (i.e. the output power rating of the device) can be achieved only at a particular load, which is usually referred to as the optimum load. The optimum load consists of two partsthe real part (the optimum conductance) and the imaginary part (the optimum susceptance). With the optimum susceptance compensating the output capacitance of the active device, the optimum conductance determines the relationship between the output voltage swing and the current swing at the load and thereby the efficiency. As mentioned before, for a linear class-B operation, the optimum conductance can be determined by the load-line equation:
Ropt =
Vdc I max / 2
(Equation 5.1)
At such optimum conductance, a maximum unclipped (linear amplification) voltage swing is generated by the maximum current swing (the fundamental component of the drain current). Therefore, a maximum output power is achieved for a proper input power that induces the maximum current swing, and so is the optimum efficiency for a certain dc supply. In some applications, signals with a varying envelope need to be amplified. When the input power decreases, with an ideal strongly nonlinear trans-conductive model assumed (which has a perfectly linear region between the cutoff and saturation points), the induced drain current will drop in proportion to the envelope of the input signal. If the load is still fixed at the optimum conductance for the maximum output power, the output voltage swing generated at the load will shrink proportionally. By contrast, for the dc components, although
77
the dc current also goes down with the input power, the dc voltage still remains at the dc supply. As a result, the output RF power drops more rapidly than does the dc power, which means sharp degradation of the efficiency. In order to avoid the decline of the efficiency, the real part of the load can be accordingly modulated (more specifically, the conductance should be reduced proportionally while the susceptance remains fixed) so that the maximum output voltage swing (double of the dc supply voltage for class-B operation) is restored. For an idealized device in class-B operation, the optimum efficiency at the maximum output power should be completely restored at an output power backed off. For an actual device, however, the original efficiency cannot be fully restored due to device nonlinearity, device parasitics, and other factors. Yet the efficiency can still be improved significantly by load modulation. Such efficiency performance under load modulation is of great importance in some applications such as Chireixs/LINC amplifiers and Doherty amplifiers. The efficiency performance under load modulation differs in various types of active devices that have different prices. Performance price ratio is important for commercial applications of these active devices. As a more expensive active device, GaN HEMT should, arguably, show better efficiency under load modulation than the cheaper LDMOS. This chapter is devoted to a comparison of the simulated efficiency under load modulation between GaN HEMT and LDMOS. The research goal is to find out whether GaN HEMT really outperforms LDMOS under load modulation and if it does, how much. Based on the results of this research, a better choice of active device in commercial applications can be made.
5.2
Device models
For GaN HEMT, we use the 45-watt die model CGH40060D delivered by CREE and the
corresponding package parasitics network (same as used in the design of Chireixs outphasing amplifier, see Figure 3.3) to simulate the efficiency under static load modulation. For LDMOS, a 45-watt package model NXP_BLF6G22_45_V1p0ii provided by NXP is used in the simulation. This LDMOS package model includes the bare die device as well as the package parasitics. The symbol schematic of NXP_BLF6G22_45_V1p0ii is shown in Figure 5.1. One special feature of this model is that extra pins are provided so that model users can easily access the internal gate, drain, and source of the device. According to the user guidelines of this model, these extra pins can only be connected to probe components or be
78
connected short-circuited, but nothing more is recommended.
Figure 5.1: A 45-watt LDMOS package model (Courtesy of NXP)
5.3
Simulation procedures of static load modulation

The static load modulation simulation is carried out for each model in the following
procedures. (1) Determine the biases and estimate the input power (actually the available power from sourcePavs) and the optimum conductance at the internal drain (Gopt) for the maximum output power (Pmax). In a class-B operation mode, the gate of the active device should be biased at the pinchoff voltage. The drain bias is provided by a 28-volt dc supply for both models. The Pavs needed for Pmax can be estimated by using the output power rating and the power gain in the data sheet of the device model. The optimum conductance at the internal drain can be estimated by using the loadline equation:
Gopt
I max Vdc I max / 2 2P = = 2 2 = max Vdc Vdc Vdc 2
(Equation 5.2)
(2) Based the estimation of Pavs and Gopt, proper harmonic termination that can achieve good class-B waveforms are determined both at the internal gate and at the internal drain.
79
To achieve a class-B operation mode, besides proper biases, proper harmonic termination both at the input and at the output are also needed. For an idealized device, in order to achieve a class-B operation, whose features involve a perfect sinusoidal drain voltage waveform and a halfwave-rectified sinewave drain current, all higher harmonics should be shorted both at the internal gate and at the internal drain. For actual devices, however, things are somewhat different. First of all, because of package parasitics, sometimes it is impractical to provide perfect harmonic short at the internal gate and the internal drain. In practice, we can only provide harmonic short as perfect as possible by tuning the source impedances and the load impedances outside the package because the internal pins of the actual device are inaccessible. Second, even if we can provide nearly perfect short for all the higher harmonics at the internal gate, this does not necessarily lead to a good class-B drain current waveform. The reason is that due to device nonlinearity, in order to achieve a good halfwave-rectified sinewave drain current, some harmonics need to be provided at the internal gate. Therefore, in our simulation, nearly perfect harmonic short is provided at the internal drain, which ensures a perfect sinusoidal drain voltage waveform; at the internal gate, instead providing harmonic short, we tune the harmonic termination until the drain current waveform looks as close to a class-B waveform (a perfect halfwaverectified sinewave) as possible. Before tuning the harmonic termination, an input conjugate match at fundamental frequency should be realized so that the actual input power is approximately equal to Pavs. When tuning the harmonic termination, we also need to ensure that the active device is not overdriven because we want to base the comparison on a linear class-B operation, not an overdriven one. Whether the device is overdriven or not can be discovered by checking the swing of the drain voltage. If the device is overdriven, the amplitude of the drain voltage will be larger than the dc supply voltage. In that case, Pavs needs to be reduced accordingly so that the device is not overdriven. With a proper Pavs, proper harmonic termination, and a proper load conductance, the efficiency and the output power should be comparable to the optimum values, at least not much lower than the optimum values. (3) Based on the input match and the harmonic termination determined previously, loadpull simulations are performed at several different Pavs levels to determine the best Pavs and the optimum internal load (seen by the internal drain) for the optimum efficiency at the maximum output power in a linear class-B operation. (4) Estimate the Pavs level required for each output power back-off level. Under the
80
optimum load condition, a Pout -Pavs characteristic curve can be plotted by sweeping Pavs. The Pavs level required by a particular output power back-off can be estimated by this characteristic. (5) Based on the estimate of the Pavs levels, Pavs is reduced and the conductance of the load is accordingly modulated while the susceptance is kept unchanged so that a particular target output power back-off is achieved. Tune the conductance and adjust the source power until an optimum efficiency is obtained at the target output power. Alternatively, a load-pull simulation can be performed at the estimated Pavs to determine the optimum load for the optimum efficiency at the target output power. Two approaches, tuning and load-pull simulation are equivalent in principle. No matter which approach is adopted, special attention needs to be paid on ensuring that the device is not overdriven. (6) Repeat step (5) until enough simulated data points are obtained to plot the efficiency as a function of the output power back-off into a smooth curve. Because the load conductance is modulated point by point at each output power back-off level, not continuously or dynamically, this kind of load modulation is referred to as static load modulation.
5.4
GaN HEMT 45-watt model
5.4.1 Harmonic termination

The biases of the GaN HEMT 45-watt device are identical to those used in the Chireixs outphasing amplifier design. From the data sheet of the GaN HEMT 45-watt model, we know that this device has an output power rating of 45 watts (or 46.6 dBm) and a power gain of about 10 dB. Therefore, an estimate of the input power for the maximum output power is about 36 dBm. An estimate of the optimum conductance at the internal drain can be calculated by using the loadline equation:
Gopt =
2 Pmax 2 45 = = 0.115 Vdc 2 282
(Equation 5.3)
The circuit used for tuning harmonic termination is shown in Figure 5.2. At the input, variable Zsource provides the source impedance of the power source at the fundamental frequency while impedance array Z_s provides all the higher harmonic impedance. Impedance array Z_series is used to ensure that Zsource functions only at the fundamental frequency. At the output, reflection coefficient array LoadTuner provides the fundamental load as well as the loads at all the higher harmonics. Variable SourceRX and LoadRX are
81
used to tune the harmonic termination at the input and at the output. Besides the common components used for load-pull simulation (HB1, Sweep1, SweepEquations, and
ImpedanceEquations), an additional reflection coefficient array LoadTuner0 is used to set
the optimum load (S11_opt) and an additional harmonic balance component HB0 is used to simulate the performance at such optimum load. A large signal S-parameter component HB2 is used to check the input conjugate matching.
Figure 5.2: Circuit schematic for the static load modulation of GaN model
The simulation results are shown in Figure 5.3. Nearly perfect harmonic short has been provided at the internal drain. As a result, the drain voltage is a perfect sinusoidal waveform that has an amplitude about 27.6 volts (under 28 V), meaning the device is not overdriven. In
82
order to ensure the device is not overdriven, the source power has been reduced to 34.65 dBm and the load conductance has been increased to 0.120. The actual output power at the internal drain is about 45.8 watts, slightly higher than the output power rating of the device because the package parasitics cause some loss. It can be seen that the relationship between the actual output power and the actual drain voltage amplitude agrees with the loadline equation pretty well:
Gopt =
2 Pdrain 2 45.8 = = 0.120 Vdrain 2 27.62
(Equation 5.4)
Because the waveform of the drain current is far from a halfwave-rectified sinewave, only by checking the drain current waveform, it is difficult to determine when the harmonic termination is good enough. So, in practice, after we have achieved nearly perfect harmonic short at the internal drain, we tune the harmonic termination at the internal gate until the best attainable efficiency at the maximum output power is obtained.
Figure 5.3: GaN model simulation results of harmonic termination tuning
5.4.2 Optimum load

Based on the harmonic termination determined from above, load-pull simulations are performed at several different Pavs to find the best Pavs and the optimum load for the maximum output power. The circuit used in the load-pull simulation is identical to that in
83
Figure 5.2. The simulation result of the optimum load is shown in Figure 5.4. The efficiency at the optimum load is slightly better than the one obtained previously.
Figure 5.4: GaN model simulation results at the optimum load for maximum output power
One thing needs to be explained here is that the susceptance in the optimum load for the maximum output power is not necessarily an optimum one for the static load modulation. In the static load modulation, the susceptance of the load is kept fixed while the load conductance is modulated to improve the efficiency at each output power back-off level. The precondition of static load modulation is the load susceptance can fully compensate the output capacitance of the active device so that it can be fixed when the load conductance is modulated. Such susceptance can be regarded as an optimum susceptance for the whole output power back-off range and its accuracy is key to the success of the static load modulation. However, the susceptance in the optimum load found from load-pull simulation is not necessarily the optimum one for static load modulation. To obtain a more accurate value of such optimum susceptance, load-pull simulations can be performed at several output power back-off levels to find the optimum load for the best efficiency. The susceptance of the resulting loads should be approximately constant, which can be used as a more accurate estimate of the optimum susceptance for the static load modulation. If such optimum susceptance is used at the maximum output power, the efficiency will
84
be lower than the optimum one obtained at the optimum load obtain from load-pull simulation because the load deviates from the optimum load. Then the load conductance can be adjusted so that an efficiency as close to the optimum one as possible is achieved. This final combination of the optimum susceptance for static load modulation and the adjusted conductance, i.e. the final load admittance, can be regarded as an optimum one for the static load modulation. At this optimum load, the simulated result is shown in Figure 5.5.
Figure 5.5: GaN model simulation results at the optimum load for static load modulation
At such optimum load, the Pavs is swept to achieve a Pout -Pavs characteristic, based on which an estimate of Pavs needed for a certain output power back-off level can be made. This Pout -Pavs characteristic is presented in Figure 5.6. Also, a curve of the efficiency as the function of the output power back-off is presented in the same figure.
85
Figure 5.6: Pout -Pavs characteristic of GaN model and efficiency versus output power without load modulation
5.4.3 Static load modulation

Based on the Pout -Pavs characteristic, static load modulation is carried out for the GaN model. The circuit used in static load modulation is the same as shown in Figure 5.2. The simulation results are shown in Table 5.1 and Figure 5.7. In the static load modulation, 10 output power back-off levels, from -1 dB to -10 dB, have been simulated. Pin is the real input power, which remains close to Pavs in the whole output power back-off range, meaning a good input conjugate match has been realized. S11opt is the reflection coefficient of the fundamental load at the output whereas Yd is the load admittance seen by the internal drain. In the simulation, we tune S11opt to achieve the required Yd. Vd[1] is the fundamental component of the voltage at the internal drain, which can indicate whether the device is overdriven or not. As can be seen from the comparison between the efficiency in the static load modulation and non-modulation, load modulation can significantly improve the efficiency of this GaN device when the output power backs off.
Table 5.1: Simulation data of static load modulation for GaN model
Pout (dBm) 46.60 45.60 44.60 43.60 42.60 41.60
Pavs (dBm) 34.18 33.69 33.35 33.11 32.84 32.40
Pin (dBm) 34.17 33.62 33.22 32.92 32.58 32.05
Efficiency (%) 74.4 75.3 75.4 74.8 73.5 71.2
S11opt
-0.809-j*0.031 -0.813+j*0.011 -0.824+j*0.048 -0.840+j*0.080 -0.859+j*0.104 -0.874+j*0.121
Yd (S) 0.125-j*0.092 0.098-j*0.092 0.078-j*0.092 0.061-j*0.092 0.049-j*0.092 0.040-j*0.092
Vd[1] (V) 27.02 27.23 27.28 27.36 27.30 26.77
86
40.60 39.60 38.60 37.60 36.60
31.36 30.57 30.17 29.85 29.41
30.93 30.13 29.69 29.32 28.85
69.1 67.5 66.1 64.8 63.3
-0.880+j*0.126 -0.888+j*0.133 -0.901+j*0.143 -0.914+j*0.151 -0.923+j*0.158
0.038-j*0.092 0.034-j*0.092 0.028-j*0.092 0.023-j*0.092 0.020-j*0.092
24.75 23.26 22.70 22.33 21.66
Figure 5.7: Static load modulation result of GaN model (Red curve, blue one is the efficiency without load modulation)
5.5
LDMOS 45-watt model

For the LDMOS 45-watt model, the procedure of static load modulation is almost the
same as that for GaN HEMT model. Therefore, detailed procedure description will be omitted here. Instead, key steps and important results are provided in the following sections.
5.5.1 Harmonic termination

From the DC simulation, we found the pinch-off voltage of the LDMOS 45-watt device is about 2.0 volts. So the gate is biased at 2.0 volts. The drain of the device is also biased at 28 volts. From the data sheet of the LDMOS 45-watt model, we know that this device has an output power rating of 45 watts (or 46.6 dBm) and a power gain of about 18 dB. Therefore, an estimate of the input power for the maximum output power is about 28.6 dBm. An estimate of the optimum conductance at the internal drain can be calculated by using the loadline equation:
Gopt =
2 Pmax 2 45 = = 0.115 Vdc 2 282
(Equation 5.5)
87
The circuit used for tuning harmonic termination is shown in Figure 5.8.
Figure 5.8: Circuit schematic for the static load modulation of LDMOS model
5.5.2 Optimum load

The circuit used in the load-pull simulation is identical to that in Figure 5.8. The simulation result at the optimum load is shown in Figure 5.9.
Figure 5.9: LDMOS model simulation results at the optimum load for maximum output power
88
5.5.3 Static load modulation

Simulation results at the optimum load for the static load modulation is presented in Figure 5.10.
Figure 5.10: LDMOS model simulation results at the optimum load for static load modulation
At this optimum load, the Pavs is swept to achieve a Pout -Pavs characteristic, which is presented in Figure 5.11. This characteristic is used to estimate the Pavs needed for each output power back-off level in the static load modulation.
Figure 5.11: Pout -Pavs characteristic of LDMOS model and efficiency versus output power without load modulation
89
The simulation results of the static load modulation are shown in Table 5.2 and Figure 5.12. The simulation results show that with load modulation, the efficiency of the LDMOS device has been considerably improved in the output power back-off range.
Table 5.2: Simulation data of static load modulation for LDMOS model
Pout (dBm) 46.6 45.6 44.6 43.6 42.6 41.6 40.6 39.6 38.6 37.6 36.6
Pavs (dBm) 26.85 25.25 23.80 22.40 21.15 19.95 18.90 17.80 16.85 15.90 15.10
Pin (dBm) 26.85 25.25 23.79 22.37 21.09 19.85 18.75 17.56 16.54 15.49 14.57
Efficiency (%) 70.6 69.4 67.6 65.3 62.6 59.5 56.1 52.7 49.1 45.3 41.5
S11opt
-0.789-j*0.060 -0.783-j*0.016 -0.785+ j*0.028 -0.794+ j*0.068 -0.807+ j*0.101 -0.824+ j*0.130 -0.838+ j*0.154 -0.854+ j*0.167 -0.870+ j*0.184 -0.883+ j*0.193 -0.898+ j*0.204
Yd (S) 0.135-j*0.285 0.108-j*0.285 0.087-j*0.285 0.071-j*0.285 0.059-j*0.285 0.049-j*0.285 0.041-j*0.285 0.036-j*0.285 0.030-j*0.285 0.027-j*0.285 0.023-j*0.285
Vd[1] (V) 27.29 27.32 27.32 27.13 26.81 26.46 26.02 25.09 24.77 23.95 23.87
Figure 5.12: Static load modulation results of LDMOS model (Red curve, blue one is the efficiency without load modulation)
90
5.6
Comparison and conclusion

After achieving the static load modulation results of these two active devices, a
comparison of the efficiency between these two models can be made, which is shown in Figure 5.13. It can be seen from this figure that under static load modulation, the efficiency of GaN device is considerably higher than that of LDMOS device not just at the maximum output power but also in the output power back-off range. The more the output power backs off, the bigger the efficiency difference is. So the conclusion is that as a type of active devices based state-of-the-art Gallium Nitride technology, GaN HEMT devices significantly outperform LDMOS devices under the condition of static load modulation. Such outstanding efficiency performance gives a reasonable explanation why GaN HEMT devices are much more expensive than LDMOS devices.
Figure 5.13: Efficiency comparison between GaN and LDMOS under static load modulation
91
92
Chapter 6. Conclusions and suggestions
Chapter 6 Conclusions and suggestions

6.1 Conclusions
In this M.Sc. project, three closely related topics in the area of power amplifier have been investigated. Firstly, the principle of Chireixs outphasing or LINC operation was studied, and based this operation principle and GaN HEMT devices, a Chireixs outphasing amplifier for base station applications was designed which consists of two saturated class-B PAs and a power combiner, and a prototype of this outphasing amplifier was fabricated and measured. Secondly, two potential approaches for implementing dual-band Chireixs outphasing amplifier were proposed. Lastly, a comparison of the simulated drain efficiency under static load modulation between GaN HEMT model and LDMOS model was made to provide a guideline on active device choice for commercial applications. The accomplishment of the implementation of the Chireixs outphasing amplifier shows that as a promising efficiency enhancement technique, Chireixs outphasing operation, along with the load compensation, can truly significantly improve the efficiency over a wide output power back-off range. Highly efficient PA cells based on excellent active devices, a suitable power combiner, and proper load compensation are three important keys to a successful implementation of Chireixs outphasing amplifier. For multi-band applications, two embryonic ideas for implementing dual-band Chireixs outphasing amplifiers were put forward. Simulation results show that both of these dual-band ideas are feasible, at least on the conceptual stage of the design process. Although there is still a long way to go from the conceptual stage to practical implementation of dual-band Chireixs outphasing amplifier and much more needs to be taken into consideration in designing a real multi-band Chireixs outphasing amplifier, these two dual-band concepts can be seen as a good starting point toward practical solutions to dual-band Chireixs outphasing amplifiers. As for the efficiency under the condition of static load modulation, GaN HEMT devices show a great advantage over LDMOS devices. In commercial applications where very high efficiency is needed, GaN HEMT devices are a good choice, but high cost of active device is 93
Chapter 6. Conclusions and suggestions
the price to pay. By contrast, LDMOS devices are cheaper than GaN HEMT devices. Yet they generally exhibit considerably lower efficiency than do GaN HEMT devices under the condition of static load modulation.
6.2
Suggestions
Some work of this project deserves more effort because it is very likely to achieve even
better results. For example, in our design of Chireixs outphasing amplifier, a general saturated class-B mode has been realized in the PA cell. However, a class-F mode that normally exhibits higher efficiency than class-B mode is also suitable for Chireixs outphasing operation. Therefore, a Chireixs outphasing amplifier design based on class-F operation mode, which may show even better performance, deserves an endeavor. Other work accomplished in this project represents the starting points of several new topics. Proper load compensation is an important key to a high performance Chireixs outphasing amplifier. In our work, the load is compensated only at a fixed outphasing angle, at which excellent efficiency is achieved. It is apparent that better overall efficiency can be achieved if the load can be adaptively compensated according to the change of the outphasing angle. Thus, adaptive load compensation may represent a promising technique to further enhance the overall efficiency of a Chireixs outphasing amplifier. Last but not the least, the design and implementation of practical multi-band Chireixs outphasing amplifier is another interesting novel topic that is worthy of exploration.
94
Chireix's/LINC Amplifier for Base Station Applications Using GaN Devices with Load Compensation
References
[1] H. Chireix, High Power Outphasing Modulation, Proc. IRE, vol. 23, no. 11, pp. 13701392, Nov. 1935. [2] D. C. Cox, Linear Amplification with Nonlinear Components, IEEE Transactions on Communication, vol. COM-22, no. 12, pp. 1942-1945, Dec. 1974. [3] J. Yao, S. I. Long, Power Amplifier Selection for LINC Applications, IEEE Transactions on Circuits and SystemsII: Express Briefs, vol. 53, no. 8, pp. 763-767, Aug. 2006 [4] F. H. Raab, Efficiency of Outphasing RF Power Amplifier Systems, IEEE Trans. Communications, vol. COM-33, no. 10, pp. 1094-1099, Oct. 1985. [5] F. H. Raab, Class-F Power Amplifier with Maximally Flat Waveforms, IEEE Transaction on Microwave Theory and Techniques, vol. 45, no. 11, pp. 2007-2012, Nov. 1997 [6] I. Hakala et al, A 2.14-GHz Chireix Outphasing Transmitter, IEEE Transaction on Microwave Theory and Techniques, vol. 53, no. 6, pp. 2129-2138, Jun. 2005 [7] R. Negra et al, Concurrent Dual-Band Class-F Load Coupling Network for Applications at 1.7 and 2.14 GHz, IEEE Transactions on Circuits and SystemsII: Express Briefs, vol. 53, no. 3, pp. 259-263, Mar. 2008 [8] Xuejun Zhang, et al, Design of Linear RF Outphasing Power Amplifiers, Artech House, 2003 [9] David M. Pozar, Microwave Engineering, John Wiley & Sons, Inc. 1998. [10] Steve Cripps, RF Power Amplifiers for Wireless Communications, Artech House, 1999.
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Chireixs / LINC Power Amplifier for Base Station Applications Using GaN Devices with Load Compensation

Delft University of Technology, September 2008.

Department of Electrical Engineering

Department of Electrical Engineering

Department of Electrical Engineering

Department of Electrical Engineering

Department of Electrical Engineering

Figure 1.1: Efficiency and linearity trade-off in RF power amplifiers

Chapter 2. Chireixs outphasing amplifier

Chapter 2 Chireixs outphasing amplifier

Figure 2.1: Simplified block diagram of an outphasing system

Chapter 2. Chireixs outphasing amplifier

2.1.1 A mathematical description of Chireix's outphasing operation

Figure 2.2: A Chireix outphasing system with a differential-topology power combiner

Chapter 2. Chireixs outphasing amplifier

Sin (t ) = E (t ) cos[t + (t )]; 0 E (t ) Em

Figure 2.3: A complex phasor representation of Chireixs outphasing operation

Chapter 2. Chireixs outphasing amplifier

Sout (t ) = S `1 (t ) S `2 (t ) = G [ S1 (t ) S 2 (t )] = G Sin (t ) = G E (t ) cos[t + (t )] (Equation 2.7)

2.1.2 Theoretical efficiency of Chireix's outphasing amplifier

Chapter 2. Chireixs outphasing amplifier

A differential-topology lossless power combiner is used for signal combination

Figure 2.4: Simplified output schematic of Chireixs outphasing system

V1 = Vo e+ j = Vo (cos + j sin ) V2 = Vo e j = Vo (cos j sin ) with Vo = Vdc and 0

Vin (t) = V (t )exp{ j (t )}; 0 V (t ) Vm

Then the differential output voltage is given by

Chapter 2. Chireixs outphasing amplifier

VL (t) = 2Vo j sin

= Av V (t ) exp[ j (t )] = Av Vin (t)

V1 cos + j sin R = RL = L (1 j cot ) V1 V2 2 j sin 2 RL

1 2sin 2 sin 2 = +j = Go + jBo Z1 RL RL 1 2sin 2 sin 2 = j = Go jBo = Y1* Z2 RL RL

2sin 2 sin 2 where Go = and Bo = RL RL

Chapter 2. Chireixs outphasing amplifier

2 2 2 2 2 2 I1 = I fund = V1Y1 = Vdc Y1 = Vdc Y2 Vdc Y (Equation 2.15)

The total DC power dissipated by the PAs is

2sin 2 RL 2sin 2 sin 2 + RL RL

Chapter 2. Chireixs outphasing amplifier

2sin 2 sin 2 and Bo = RL RL

Chapter 2. Chireixs outphasing amplifier

Y1 = Y1 + j ( Bcomp ) = Go + j ( Bo Bcomp ) = = Y2 + j (+ Bcomp ) = Go j ( Bo Bcomp ) = Y2 where Bcomp = sin 2comp RL

sin 2 sin 2comp 2sin 2 + j RL RL sin 2 sin 2comp 2sin 2 j = (Y1)* RL RL

Chapter 2. Chireixs outphasing amplifier

(2sin 2 ) + (sin 2 sin 2comp )

Chapter 2. Chireixs outphasing amplifier

2.2 A practical common-mode topology of Chireix's outphasing system

Chapter 2. Chireixs outphasing amplifier

For a quarter-wavelength line ( =90o) having a characteristic impedance Z0, its

Chapter 2. Chireixs outphasing amplifier

The voltage sources remain the same as in (Equation 2.8, thus

V1 + V2 Vo (e+ j + e j ) 2Vo cos I L = I o1 + I o2 = = = jZ 0 jZ 0 jZ 0 VL = I L RL = I1 = I 2 = 2Vo cos RL jZ 0

Chapter 2. Chireixs outphasing amplifier

2cos 2 RL 2cos 2 2 sin 2 2 ) +( ) RL RL

= PRF = Vdc 2Go

Chapter 2. Chireixs outphasing amplifier

) = Go j ( Bo Bcomp )= Y1 = Y1 + j (+ Bcomp = Y2 + j ( Bcomp ) = Go + j ( Bo Bcomp )= Y2 = where Bcomp sin 2comp RL

sin 2 sin 2comp 2cos 2 j RL RL sin 2 sin 2comp 2cos 2 + j = (Y1)* RL RL

(2cos2 ) + (sin 2 sin 2comp )

Chapter 2. Chireixs outphasing amplifier

normalized output RF power, which is illustrated in Figure 2.17.

Conditions 36 dBm 50(0.031-j0.127) ohm 0.069-j*0.103 S