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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
This project is ported to github and can be found at:
https://github.com/chiphackers/covered
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License
GNU General Public License version 2.0 (GPLv2)Follow Covered
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