Code Merge Request #30: target: arm926ejs Resolve Unable to set 32 bit software breakpoint at address for SW breakpoints (open)
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Gabriel Volpicelli wants to merge 1 commit from /u/gvolpicelli/openocd/ to master, 2024-05-17
The arm926ejs_write_memory function wil use armv4_5_mmu_write_physical to write directly to physical memory for 32 and 16 bit writes. When it does so, it bypasses the dcache. For these writes, the dcache must be invalidated, even if the dcache is in write-through mode. If the dcache is not invalidated after these physical writes, then software breakpoints will not function correctly for any code page that is already in the dcache. This produces the Unable to set 32 bit software breakpoint at address error message. The sequence of events is: arm7_9_common.c writes the breakpoint instruction to memory, arm926ejs.c performs a physical write directly to RAM, causing the cache to become incoherent, then arm7_9_common.c reads the instruction back to verify it and arm926ejs.c reads it back via the cache. This commit adds a dcache invalidate to the code path that uses armv4_5_mmu_write_physical for the MVA that was written. Another potential solution is to modify the arm926ejs_write_memory function to always perform a non-physical write and utilize the dcache write-through but this was not tested.
| Commit | Date | |
|---|---|---|
|
[9d5910]
(arm926ejs_dcache_fix)
by
gvolpicelli
The arm926ejs_write_memory function wil use armv4_5_mmu_write_physical to write directly to physical memory for 32 and 16 bit writes. When it does so, it bypasses the dcache. For these writes, the dcache must be invalidated, even if the dcache is in write-through mode. If the dcache is not invalidated after these physical writes, then software breakpoints will not function correctly for any code page that is already in the dcache. This produces the Unable to set 32 bit software breakpoint at address error message. The sequence of events is: arm7_9_common.c writes the breakpoint instruction to memory, arm926ejs.c performs a physical write directly to RAM, causing the cache to become incoherent, then arm7_9_common.c reads the instruction back to verify it and arm926ejs.c reads it back via the cache. This commit adds a dcache invalidate to the code path that uses armv4_5_mmu_write_physical for the MVA that was written. Another potential solution is to modify the arm926ejs_write_memory function to always perform a non-pysical write and utilize the dcache write-through but this was not tested. |
2024-05-17 22:04:33 | Tree |
