| Semantic zoom within a diagram of a system JL Kodosky, DW Fuller III, JN Correll, MK Shah, J Kornerup, TJ Hayles, ... US Patent 9,047,007, 2015 | 99 | 2015 |
| Timed sequence for a graphical program J Kornerup, B Shah, A Vrancic US Patent 7,761,847, 2010 | 86 | 2010 |
| Graphical program which executes a timed loop B Shah, J Kornerup, A Vrancic, JL Kodosky, ML Santori US Patent 7,574,690, 2009 | 73 | 2009 |
| Optimization of a data flow program based on access pattern information G Wang, K Ravindran, R Limaye, G Yang, A Ghosal, HA Andrade, ... US Patent 9,335,977, 2016 | 67 | 2016 |
| Diagram that visually indicates targeted execution JL Kodosky, DW Fuller III, TJ Hayles, JN Correll, JR Breyer, J Kornerup, ... US Patent 7,844,908, 2010 | 61 | 2010 |
| Graphically representing timing in a graphical program J Kornerup, JL Kodosky, HA Andrade, B Shah, A Vrancic, ML Santori US Patent 8,397,205, 2013 | 55 | 2013 |
| Synchronizing execution of graphical programs executing on different computer systems A Vrancic, J Kornerup US Patent 7,565,609, 2009 | 51 | 2009 |
| Timing wires in a graphical program J Kornerup, JL Kodosky, HA Andrade, B Shah, A Vrancic, ML Santori US Patent 8,359,567, 2013 | 47 | 2013 |
| Graphical diagram wires whose appearance represents configured semantics JL Kodosky, DW Fuller III, JN Correll, TJ Hayles, JR Breyer, J Kornerup US Patent 8,028,241, 2011 | 45 | 2011 |
| Diagram with configurable wires JL Kodosky, JN Correll, DW Fuller III, TJ Hayles, JR Breyer, J Kornerup US Patent 8,028,242, 2011 | 42 | 2011 |
| Automatically Mapping Program Functions to Distributed Heterogeneous Platforms Based on Hardware Attributes and Specified Constraints K Ravindran, HA Andrade, A Prasad, A Ghosal, TN Tran, R Limaye, ... US Patent App. 15/470,374, 2017 | 41 | 2017 |
| Developing programs in a graphical specification and constraint language K Ravindran, G Yang, J Kornerup, IC Wong, JN Correll, MJ Trimborn, ... US Patent 8,726,228, 2014 | 41 | 2014 |
| Visualization tool for viewing timing information for a graphical program J Kornerup, B Shah, A Vrancic, B Preis US Patent 7,703,034, 2010 | 39 | 2010 |
| Developing programs for hardware implementation in a graphical specification and constraint language K Ravindran, J Kornerup, R Limaye, G Yang, G Wang, JN Correll, ... US Patent 8,887,121, 2014 | 28 | 2014 |
| Timed loop with sequence frames structure for a graphical program J Kornerup, B Shah, A Vrancic, M Curtis, S Rogers US Patent 7,802,229, 2010 | 27 | 2010 |
| Data structures for parallel recursion J Kornerup The University of Texas at Austin, 1997 | 27 | 1997 |
| Developing programs for hardware implementation in a graphical specification and constraint language Via iterative estimation of performance or resource utilization G Wang, JN Correll, SB Malik, HA Andrade, NG Petersen, R Limaye, ... US Patent 8,719,774, 2014 | 24 | 2014 |
| Spatial iteration node for a graphical program J Kornerup, AP Dove, J Sumner US Patent 8,117,588, 2012 | 22 | 2012 |
| Correct and non-defensive glue design using abstract models S Tripakis, H Andrade, A Ghosal, R Limaye, K Ravindran, G Wang, ... Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011 | 22 | 2011 |
| Asynchronous Wires for Graphical Programming JL Kodosky, J Kornerup US Patent App. 11/462,393, 2008 | 20 | 2008 |
Kaushik RavindranNational Instruments R&DVerified email at ni.com
