Topical Workshop on Electronics for Particle Physics

The upcoming ProtoDUNE-II program at the CERN Neutrino Platform will consist of 2 liquid argon time projection chambers, which will serve as demonstrators of the technologies that will be used in the first 2 far detectors of the Deep Underground Neutrino Experiment (DUNE). A core component of these detectors is the cryogenic charge readout electronics, which are immersed in liquid argon along with the detectors and are responsible for reading out charge signals from the anodes of the time projection chambers. We discuss the design of these electronics and preliminary performance results from the ProtoDUNE-II assembly experience.

The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in the industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications. This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, includes an event generator, interfaces with real physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy. This contribution details the structure of the framework and describes a case study based on the LHCb VeLo upgrade II.

In this paper, we explore the transitions of low-frequency noise characteristics in high-k metal-gate bulk CMOS transistors induced by Total Ionizing Dose (TID). Due to the strong bias dependence of the noise characteristics, differentiating between noise shifts caused by the effective biasing change and the contribution of the newly generated traps becomes extremely challenging. In order to better understand the effects of irradiation, transistor noise had to be characterized at several biasing points, both in linear and saturation regions, before and after exposure to 1 Grad (SiO₂) of TID. Correlation between shifts in time and frequency domain is presented in this work, along with possible explanations for each variation that occurs. We present examples of irradiation-generated Random Telegraph Noise (RTN) defects as well as various TID effects on noise Power Spectral Density (PSD) curves with pre-existing RTN sources.

The University of Bergen is involved in developing two calorimeters: the pixel section of the Electromagnetic Forward Calorimeter for the ALICE Upgrade to be installed during LS3 for data-taking in the period 2029–2032 and the Digital Tracking Calorimeter for the proton Computed Tomography prototype. Both designs utilize pixel sensors and require a reliable connection to the readout which is positioned approximately 5 meters away. Furthermore, the structural design of these calorimeters calls for a compact layer assembly. This paper provides the strategies deployed to meet these critical requirements, focusing on the implementation of the chip-on-flex assembly, and the ultrasonic welding techniques. It further describes other design considerations essential for maintaining good signal integrity. Finally, it gives insight into the experiences and challenges faced while working with the prototypes, both in the laboratory and test beam setups.

The IGNITE project (INFN Ground-up INITiative-on micro-Electronics developments) is developing solutions on integrated micro-systems aimed at the next generation of high-luminosity experiment at the LHC. A test ASIC, designed in CMOS 28-nm technology and named Ignite-0, has been submitted for fabrication. It integrates circuital solutions suitable for pixels with timing having a pitch ranging from 45 to 55 µm. The present paper describes the criteria used in the design choices, and the expected ASIC performance as output from post-layout simulations. Perspectives on subsequent design work on 4D-tracking devices following the Ignite-0 development are also briefly described.

This contribution presents a pragmatic approach to read-out electronics for drift chambers used in particle physics experiments, specifically for the R3B experiment at GSI. The design uses discrete miniature SMD components and LVDS inputs of a low-cost FPGA to achieve a performance similar to classic ASIC solutions to the problem. The circuit comprises a high gain, low noise amplifier, a custom signal shaper, tailored to the specifics of proportional counter signals, and a leading-edge discriminator with programmable threshold. The presented approach offers an attractive solution for small to medium sized detector systems that require specialized read-out electronics but cannot afford the high cost and development effort associated with ASICs.

This paper introduces a prototype of a GaN-FET based 200 W DC-DC converter. Its design has been carried out to evaluate power density (or power dissipation and volume) and ensure minimal electromagnetic interference (EMI) issues that are commonly associated with the high switching frequency converters. To achieve this ANSYS HFSS-SiWave models have been developed to assess noise emissions based on the parasitic elements of PCB layout. Prototypes performance have been evaluated through extensive testing. This work offers insight into the potential of this technology in future physics detectors.

As part of the CMS Phase-2 upgrade, a prototype receiver for the HGCAL endcap front end has been implemented using the Serenity ATCA platform. The receiver firmware was developed to test the unpacking of data from the front-end endcap trigger concentrator ASIC (ECON-T) and measure its performance and stability. The firmware was integrated with prototype DAQ firmware as well as ancillary blocks to generate a trigger using ECON-T data, process scintillator trigger and timing distribution system, to evaluate the complete HGCAL vertical slice. The data was read out using custom 10G UDP links and upgraded to CMS DTH system at 25 Gbps. The system successfully achieved prototype TPG Stage-1 and DAQ path readout using generated beam triggers and delivered ~20 TB of data containing physics events at an average trigger rate of about 100 kHz.

The PADME experiment at LNF-INFN employs positron-on-target-annihilation to search for new light particles. Crucial parts of the experiment are the charged particle detectors, composed of plastic scintillator bars with light transmitted by wavelength shifting fibers to silicon photomultipliers (SiPMs). The location of the detector — close to a turbomolecular pump, inside a vacuum tank, and exposed to 0.5 T magnetic field — has driven the design of custom modular SiPM front-end and power supply electronics. The design of the system and its performance, confirming the desired sub-ns resolution on the reconstructed particle flying times, is shown and discussed.

It is well understood that modern physics experiments often require more Low Voltage power to be delivered to front-end electronics than was needed in past, and that the most effective and efficient means of delivering this LV power requires that the power supplies be placed as close as possible to the detector. Unfortunately, this means that the LV power supplies must be more robust and tolerant to radiation and magnetic fields typically present in such an environment. Designing a power supply capable of operating in such an environment is not a trivial task. It is first necessary to fully assess and understand these special conditions before one can begin to identify the power supply typology and components to be used. In this manuscript we will illustrate the design process of the CAEN EASY BRIC1 (B & Rad tolerant Intermediate Converter), an intermediate converter utilized to power the front-end electronics (12 V to 300 V) of the ATLAS-NSW experiment. The complete process is described, from design choice, to component selection, to circuit testing from B=0 to 1 T, and finally deployment and testing the complete power supply in an operational environment.

The hfrh-buck (high frequency radiation hardened-buck) is a radiation hardened DC/DC-converter operating at a high switching frequency of 100 MHz with a small air core inductor of 22 nH. To ensure a high radiation dose, the circuit is designed with core transistors of a 65 nm TSMC technology. By stacking the transistors of the power stage, the converter can be supplied with a voltage of up to 4.8 V. Stable operation can be achieved at an output voltage of 1.2 V with a maximum load current of 1 A. The prototype demonstrates the ability to power parallel connected hybrid-pixel modules in the innermost layers.

The BPOL12V is a DC/DC converter designed to supply power to the High Granularity Timing Detector (HGTD) as part of the ATLAS Phase II upgrade project. The HGTD operates in an environment characterized by low temperatures and a magnetic field. Ensuring the reliable functionality of the BPOL12V under such conditions is of utmost importance. This paper outlines a series of functionality tests for the BPOL12V, including efficiency, ripple, and rise/fall edge assessments across various operational scenarios. The performance of the BPOL12V consistently meets the requirements of the HGTD, whether it operates in low temperatures down to -30 °C or in the presence of a 0.4 T magnetic field.

We present the design of a prototype MAPS sensor MIC6_V1 based on a 55 nm Quad-well CMOS Image Sensor process for the CEPC vertex detector. A new node-based, data-driven, parallel readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. The size of MIC6_V1 is 2.8 mm × 2.8 mm, which contains a pixel matrix of 64 rows by 64 columns, and the pixel size is 23.6 μ m × 20 μ m. The integration time is 5 μs, and the hit arrival time measurement accuracy is 10 ns.

The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.

The ALICE collaboration is developing the Inner Tracker System 3 (ITS3), a novel detector that exploits the stitching technique to construct single-die monolithic pixel sensors of up-to 266 mm × 93 mm. ITS3 requires all hits from a particle flux of 5.75 MHz/cm² to be transmitted on-chip to one of the sensor edges. This on-chip readout must balance the resources of power consumption, dead area, and readout performance by tuning different design parameters such as on-chip memories or on-chip links bandwidth. For doing so, a model of the ITS3 on-chip readout architecture will be presented. This model combines an accurate simulation of the particle flux fluctuations expected in ALICE with a clock-accurate digital readout simulator, combining high accuracy with fast code in terms of simulation speed.

The Serenity-S1 is a production-optimised Advanced Telecommunications Computing Architecture (ATCA) processing blade based on the AMD Xilinx Virtex Ultrascale+ device. It incorporates many developments from the Serenity-A and Serenity-Z prototype cards and, where possible, adopts solutions being used across CERN. Due to the shortage of components during the recent semiconductor crisis, commonly used components in the prototypes had to be replaced by new ones after qualification. In this work, we discuss various improvements to simplify manufacturing, the performance of new components, some of the more difficult aspects of procurement, the performance of production-grade Samtec 25 Gb/s optical firefly parts, and concerns regarding the rack cooling infrastructure.

In preparation for the High-Luminosity phase of the CERN Large Hadron Collider, the Compact Muon Solenoid collaboration will replace the existing endcap calorimeters with the High Granularity Calorimeter. Considering both endcaps, this novel sub-detector will have around six million readout channels, pushing approximately 108 Tbit s^-1of usable data between the detector front-end (on-detector) electronics and the back-end (off-detector) electronics. Given the scale and complexity of the endcap calorimeter upgrade project, the electronics testing must be carefully planned. The strategy has been to split the efforts between vertical (start-to-end) and horizontal (parallelisation) test systems wherever possible. An important milestone was the development and operation of a test system that prototypes a complete vertical slice of the future endcap electronics system. For the first time, a version of a test system consisting of the full vertical electronics readout chain was successfully operated in a beam test, where it was used to acquire real physics data.

The combination of 3D tracking and high-precision timing measurements has been identified by the European Committee for Future Accelerators as a fundamental requirement to increase detection capabilities for future applications. Among others, on-chip high-quality clock is a key factor determining the overall resolution of timing ASICs. However, in large and dense chips, power-grid drops can severely affect the non-deterministic jitter of the clock, representing a limit to the performances. This contribution presents a simulation framework based on commercial tools to derive power supply-induced jitter, providing a pre-silicon methodology to assess its impact to timing indeterminism. The flow is presented together with practical examples and results.

Ongoing developments in the field of radiation-tolerant high-speed transmitters (HSTs) aim at increasing the data rates above 25 Gb/s while increasing total ionizing dose (TID) tolerance above 1 Grad. The use of half-rate architectures imposes tight constraints on clock signal quality, in particular its duty-cycle. Radiation degradation of transistors in the clock path causes duty cycle distortion (DCD), affecting the output signal quality of the HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is presented. It compensates for process voltage temperature (PVT) variations as well as radiation-induced duty-cycle distortion of the clock.

The CMS Tracker Phase 2 Upgrade for the High Luminosity Large Hadron Collider will use two module types, which contain different sensor configurations and custom ASICs. Guaranteeing the power integrity of all modules for the full lifetime of the detector is crucial for the detector performance. This article describes the historical evolution of the powering architecture, the problems encountered, and the solutions implemented for the two types of modules, as well as the final on-module powering strategy along with the data and modelling that motivated it.

We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment which will replace the present luminometer based on the BCM1F ASIC [1]. The FBCM system should provide reliable luminosity measurement with 1 ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises 6 channels of the fast front-end amplifier working in transimpedance configuration, booster amplifier, and leading edge discriminator. The complete processing chain provides an overall shaping function equivalent to the CR-RC³ filter. The paper will show the optimization of the design, overall architecture, and the detailed implementation in a CMOS 65 nm process as well as preliminary electrical performance.

The Electric Field Detector (EFD-02) on board the second China Seismo-Electromagnetic Satellite (CSES-02) will measure the electric field components at a Low Earth Orbit (LEO) over a wide frequency band (DC – 3.5 MHz) and with 1 μV/m sensitivity in the Low Frequency band. EFD-02 will measure the voltage differences between pairs of probes installed at the tips of four booms deployed from the satellite. In this article, we describe the Zynq System on Chip (SoC)-based digital hardware subsystem dedicated to signal processing, and the selected implementation strategy, which successfully complied to the specific requirements of the space mission. Furthermore, we present a comprehensive overview of the assessed instrument performance.

A data conversion and compression ASIC, named LiTE-DTU, has been developed for the upgrade of the CMS electromagnetic calorimeter (ECAL) for the High-Luminosity phase of LHC. The ASIC integrates two 12-bit 160 MS/s ADCs, a data processing unit for gain selection and data compression, and a 1.28 Gb/s serializer. The ASIC has been extensively tested in laboratory and in beam tests showing excellent yield and performance. The radiation tolerance has been verified with dedicated test campaigns for both total ionizing dose and single event effects. Results from these tests, showing the design readiness for mass production, will be presented.

The increase in the number of readout channels in new detectors, like the Micro Pattern Gas Detectors (MPGD), in the order of several millions, requires a large amount of electrical power to supply the front-end electronics, up to hundreds kW. If this power is generated at long distances from the detector, the voltage drop on the connection cables puts serious constraints to the supply current, to the wire cross-section and to the power distribution. A large amount of voltage drop on the cables, apart an increased power dissipation on wire resistance, determines regulation issues on the load in case of current transients. To mitigate these problems, a new generation DC/DC converter, working in a heavily hostile environment and with a power density greater than 200 W/dm³, was developed. It is modular, with up to four independent modules, eight channels each, collected in a water-cooled crate, and can supply the load with an adjustable 10 to 12 V output up to 170 W per channel. In this contribution, the design constraints of such a converter are analysed, taking as a basis the environmental, electrical and mechanical requirements of the ATLAS New Small Wheel (NSW) project. Thermal considerations require the converter to be water-cooled, and the dimensional constraints impose the adoption of an innovative design to convey the dissipated heat towards the heat exchanger. The control and monitoring system allows for the full remote management of the converter. Main electrical parameters were measured and are reported. The converter was also characterized in a harsh working environment, with radiation tests in the CERN CHARM facility beyond the limits estimated for ten years operation in ATLAS, and with magnetic field tests in various orientations, using different magnets at CERN up to 1.3 T. A better common mode noise filtering design improvement was implemented after the first characterization. Final performance measurements after the modifications are also reported.

Targeting on low power consumption and high spatial resolution, the CPV-4 SOI pixel sensor has been developed. Its pixel circuit requires about 120 transistors to implement the analog-digital mixed signal processing functionality within a compact pixel area of 17 μm × 21 μm. By utilizing 3D vertical integration, sensing diode and analog front-end are realized in the lower-tier chip, while hit information storage and sparse readout are achieved in the upper-tier chip, thereby minimizing its pixel size and power consumption. This work presents the pixel circuit design and the test results on the completed 3D chips. The feature of SOI pixel process and the 3D integration are also highlighted in this article.

Early measurements on monolithic pixel sensor prototypes in the TPSCo 65 nm technology indicate a different response and radiation tolerance (up to 5×10¹⁵ 1 MeV n_eq cm) for different sensor layout and process variants, illustrating the importance of layout and process in the path towards increased sensor radiation tolerance. Using these measurement results, TCAD simulations provide more insight to link the macroscopic behaviour of specific sensor variants to the details of its structure. With this insight we can propose a new variant combining the advantages of several measured variants as a path to even better radiation tolerance for the next iteration.

High-speed multichannel ADCs are costly and require complex FPGA or MCU firmware to communicate with them. The Multi-Voltage Thresholding (MVT) approach can replace to some extent an external ADC by harnessing the internal FPGA resources, thus reducing costs and complexity. The MVT approach needs only a few low-cost external components. The focus of the contribution is presenting an open-source IP-Core that implements the MVT approach and simplifies its implementation on a standard FPGA. The contribution also provides an overview of characterization measurements and specific calibration method. Our example application demonstrates the viability of the developed IP-Core for signal acquisition from multiple SiPMs.

The ALICE ITS3 is a novel vertex detector replacing the innermost layers of ITS2 during LS3. Composed of three truly cylindrical layers of wafer-sized 65 nm stitched Monolithic Active Pixel Sensors, ITS3 provides high-resolution tracking of charged particles generated in heavy-ion collisions. This contribution presents an overview of the ITS3 detector, highlighting its design features, integration and cooling, and the ongoing development towards the final sensor. Furthermore, the paper introduces the off-detector service electronics, which play an essential role in the readout, control, and power supply of the detector.

The drift chambers of the HADES experiment at SIS-18 at GSI, Darmstadt/Germany, form the main tracking system of the spectrometer. Designed more than twenty years ago, the whole front-end electronics chain is being replaced with state-of-the-art electronics to cope with the increasing failure rate of the old electronics and with advanced requirements of the experiment, e.g. the trigger rate. The new analog signal processing is based on the PASTTREC ASIC, developed for the Straw Tube Tracker of the PANDA Experiment. The digitization of data happens in FPGA-based TDCs. The main challenges of the project are the strict spatial constraints given by the experiment setup to place the front-end boards and the noise sensitivity of the large area gas detectors. In addition, the power consumption needed to be kept low due to thermal constraints.

Starting in 2029, the High Luminosity LHC (HL-LHC) at CERN is projected to achieve unparalleled instantaneous luminosity (7.5 × 10³⁴ cm^-2s^-1) for an integrated luminosities of 4500 fb^-1. To cope with the extreme conditions of 200 collisions per bunch crossing (pile-up), both on-detector and off-detector electronics of the CMS Electromagnetic Calorimeter (ECAL) will be upgraded. The new system will incorporate a dual-gain trans-impedance amplifier alongside an Application-Specific Integrated Circuit (ASIC) that includes dual 160 MHz ADC channels and features for gain selection and data compression. The lead tungstate crystals and avalanche photodiodes (APDs) will remain in service due to their proven reliability. To counteract the noise amplification in the APDs, attributed to radiation-induced dark currents, the operational temperature of the ECAL will be reduced from 18°C to roughly 9°C. Preliminary tests of these new electronics have yielded promising results. During tests beams at the CERN H4 beamline using an electron beam, the new electronics met both required energy resolution and linearity and achieved a timing resolution of 30 ps for energies above 50 GeV.

The Level-1 trigger scouting system of the CMS experiment aims at intercepting the intermediate data produced by the L1 trigger processors before the final trigger decision. This system can be complemented by adding the raw stream of data collected from the detector front-end, whenever the throughput is manageable. In this work, the triggerless readout of the CMS Drift Tubes (DT) detector is presented. This is realized by reading a sector of the DT which has been equipped with the preproduction of Phase-2 upgrade front-end boards. A Xilinx VCU118 acts as a concentrator of the Phase-2 demonstrator lpGBT links and transmits data to a server via 100G TCP/IP. First results coming from a test-stand mimicking the sector demonstrator are shown.

The High Luminosity Large Hadron Collider (HL-LHC [1]), an upgrade of the LHC, is set to become operational in 2029, aiming to achieve instantaneous luminosities 5–7.5 times larger than the nominal value of the LHC. However, unlocking the full physics potential at this much higher luminosity level necessitates a tenfold increase in the data bandwidth processed by ATLAS. This poses significant challenges to the design of the Trigger and Data Acquisition systems. To address these challenges, a baseline architecture has been chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger known as the Level-0 Trigger. This trigger has a maximum rate of 1 MHz and a latency of 10 μs. Central to this upgrade is the inclusion of a new subsystem — the Global Trigger [2]. This component performs complex algorithms, akin to those currently used in Phase-I high-level trigger software (such as Topoclustering), on full-granularity calorimeter data. The Global Trigger is divided into three sublayers: the Multiplexer Processor (MUX) layer, the Global Event Processor (GEP) layer, and the Global to Central Trigger Processor [3] interface (gCTPi). A full-function Global Common Module (GCM) hardware prototype has been designed to fulfill the requirements of all three sublayers of the Global Trigger, featuring different firmware loads. This GCM prototype, based on the ATCA [4] front board form factor, incorporates two of the latest AMD (Xilinx) Versal Premium devices VP1802 [5]. These devices boast double the density of the Virtex UltraScale+ FPGA VU13P used in the previous design [6] and include an integrated SoC with a completely new architecture. To handle high-speed I/Os, this GCM prototype employs twenty 12-channel 25.7 Gb/s FireFly [7] optical engines. The estimated maximum power consumption of this GCM prototype is 400 W, which falls within the cooling capabilities of the ATLAS ATCA shelf. To ensure power integrity, signal integrity, and thermal performance, extensive PCB simulations and thermal simulations have been done to guide the layout design of the GCM prototype. This paper provides an in-depth overview of the design process for this full-function GCM prototype hardware, with a particular focus on technology choices and simulation results.

The Beam Loss Monitoring system plays a crucial role in the CERN's Super Proton Synchrotron beam monitoring and machine protection. With the upcoming renovation of the system, the acquisition electronics can be based on an innovative ASIC designed by CERN. This paper presents the development of the control and digital processing electronics for this BLMASIC, reviews the architecture and design choices, discusses implementation details, including the controls and redundancy schemes, and highlights some preliminary results. The conclusion outlines the future development steps, and emphasises the interest of this simple and robust architecture using LpGBT and VTRx for critical systems.

Arrays of superconducting sensors enable particle spectrum analysis with superior energy resolution. To efficiently acquire data from frequency multiplexed sensors, the readout electronics operating at room temperature must perform multiple tasks, such as low-noise probe tone generation, frequency demodulation, and data decimation. We designed a Software-Defined Radio (SDR) system composed of an MPSoC board, an analogue-digital conversion stage, and a radio frequency front-end mixing stage to meet the system requirements of 4 GHz instantaneous bandwidth and real-time data analysis. Nevertheless, utilising a Radio Frequency System-on-Chip (RFSoC) could simplify the overall system by integrating the conversion stage. This work investigates the applicability of RFSoCs for the aforementioned use case.

We present first results obtained with a prototype 4D-tracking demonstrator, using sensors and electronics developed within the TimeSPOT project, and tested on a positive charged pion beam at CERN SPS. The setup consists of five small tracking layers in a row, having area of about 3 mm² each, three of which equipped with 3D-trench silicon sensors and two with 3D-column diamond sensors. The five layers are then read-out by a KC705 Xilinx board on a PC. We describe the demonstrator structure and operation and illustrate preliminary results on its tracking capabilities.

The ePIC experiment at the future Electron-Ion Collider (EIC) aims to use silicon photomultipliers (SiPMs) as the photodetector technology for the dual-radiator ring-imaging Cherenkov detector (dRICH). Despite their advantages for this low light application and insensitivity to high magnetic fields, SiPMs are sensitive to radiation and require rigorous testing to ensure that their single-photon counting capabilities and dark count rate are kept under control over the years of operation. The presented results show the successful use of a complete prototype readout chain based on the ALCOR chip for SiPM characterization measurements and assembled in an optical plane for test-beam measurements using the dRICH prototype.

The LHCb Experiment is commissioning its first upgrade to cope with increased luminosity of LHC Run3, being able to improve on many world-best physics measurements. A new scintillating fiber-based tracker (SciFi) replaced the outer and inner trackers, providing improved spatial resolution and granularity for the new LHCb trigger-less era, with a readout capable of reading zero suppressed data from ~524k channels at 40 MHz. The fully automated calibration of SciFi Front-End Electronics is based on dedicated software tools and operational procedures, validated during SciFi commissioning. This paper describes the design, implementation, and calibration of SciFi electronics and presents results showing the detector performance after commissioning.

Pioneering physics experiments require increasingly faster data transfers and high-throughput electronics, which drives the research towards a new class of serialisers and optical links. In this framework, the DART28, a 100 Gbps radiation tolerant serialiser and driver, has been designed in 28 nm CMOS technology, submitted in April and delivered in August 2023. The development has been coupled with an FPGA based emulation, which provided an early assessment of its behaviour, a scalable system-level demonstrator and an effective evaluation tool for compatible commercial solutions. The challenges faced in this research and the architecture of both the hardware setup and the firmware will be described.

The integration of IoT infrastructure in the context of particle accelerators promises numerous benefits (reduced costs and maintenance time, increased deployment). However, the use of microcontroller units (MCUs), typical of IoT systems, can potentially compromise future accelerator availability performances. This paper presents Software Mitigation Schemes (SMS) designed to improve the availability performance of MCU-based systems under radiation. Their effectiveness is demonstrated through a radiation test on a CERN Wireless IoT Radiation Monitoring system, also called BatMon. The results underline the IoT devices' feasibility as a viable solution for high-distribution systems in the High-Luminosity Large Hadron Collider (HL-LHC) or Future Circular Collider (FCC).

The ATLAS Strip Tracker for HL-LHC is composed of individual modules that contain silicon sensors and front-end electronics. These modules are then mounted onto carbon-fiber substructures, hosting up to 14 modules per side. At the end of these substructures, an EoS card connects up to 28 data lines to the lpGBT ASICs and the VTRX+ module, which provide data serialization and 10 Gb/s optical data transmission to the off-detector systems, respectively. The EoS card is powered by a dedicated Dual-Stage DC-DC converter. With the EoS project moving into the production stage, this contribution summarizes the quality assurance and quality control performed during the pre-production phase.

The RHIC interaction rate at sPHENIX will reach around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200 to fit the DAQ bandwidth of 15 kHz. Some critical measurements, such as heavy flavor production in pp collisions, often require the analysis of particles produced at low momentum. This prohibits adopting the traditional approach, where data rates are reduced through triggering on rare high momentum probes. We explore a new approach based on real-time AI technology, adopt an FPGA-based implementation using a custom designed FELIX-712 board with the Xilinx Kintex Ultrascale FPGA, and deploy the system in the detector readout electronics loop for real-time trigger decision.

We present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine card for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics experiments at CERN and we show the addition of new features and support for new protocols in the firmware of the controller mezzanine card.

The paper presents the Dual Use Driver (DUDE) for high speed links, a circuit designed for the Demonstrator ASIC for Radiation-Tolerant Transmitter in 28 nm CMOS (DART28) developed under the EP-R&D programme on technologies for future high energy physics experiments. The driver operates at 25.6 Gbps and it allows driving both 100 Ω transmission lines and optical Ring Modulators (RMs) integrated in a photonics integrated circuit (PIC). The driver includes configurable pre-emphasis. The device will allow to demonstrate the feasibility of wavelength division multiplexing (WDM) optical links operating with bandwidths in excess of 100 Gbps per fiber that are capable of sustaining total ionizing radiation doses up to 10 MGy.

The characterization of compact non-traveling-wave Mach-Zehnder modulators for optical readout in high-energy physics experiments is reported to provide power-efficient alternatives to conventional traveling-wave devices and a more resilient operation compared to ring modulators. Electro-optical small-signal and large-signal measurements showcase the performances of custom NTW-MZMs designed and fabricated in iSiPP50G IMEC's technology in the framework of INFN's FALAPHEL project. Bit-error-rate results demonstrate their potential suitability for optical links up to 25 Gb/s when equipped with either conventional deep-etched or radiation-hardened shallow-etched free-carrier-based phase shifters.

This study evaluates the lifetime and aging process of the aluminium electrolytic capacitors to be used in the new protection systems of the High Luminosity LHC superconducting magnets. The accelerated testing and analysis of several groups of capacitors aged for more than one year provided insights into their expected lifespan and aging process. The results obtained have practical implications for maintenance and replacement schedules, as well as for selection and acceptance of capacitors for new Heater Discharge Power Supplies (HDS) equipment. The knowledge gained from this study ensures the safety and reliability of the LHC and its electronic components.

We present details on the new Level-1 Global Trigger at CMS for the upcoming high-luminosity operation of the LHC. Our focus is on the newly developed firmware, which employs a bottom-up generic approach to enhance menu adaptability and accommodate the increase in upstream data. We also highlight our efficient pipelining strategy that ensures excellent routability at 480 MHz. Furthermore, we discuss the firmware implementation for three prototypes targeting Serenity boards, together with their current and future testing and validation endeavours.

A new Constant Fraction Discriminator with additional Time over Threshold measurement capabilities will be presented. It operates in a wide dynamic range of 1:150, with an excellent time resolution of better than 70 ps over one order of magnitude of the input signals. It is highly customizable for different signal shapes and thresholds, using remotely-programmable parameters for Detector Control System commands. Two outputs, each in the Nuclear Instrumentation Module and Low Voltage Differential Signaling standards, provide a precise signal arrival time and Time over Threshold information with programmable thresholds. The technical specification and performance measured with cosmic rays and in the high-intensity NA62 experiment will be reported.

The Level-0 endcap muon trigger system for the ATLAS experiment at the HL-LHC, which performs a fast muon reconstruction using the Thin Gap Chamber (TGC), is being developed to cope with more than three times higher luminosity environment and achieve a better performance. The efficiency in the high-p_T region was found to be 9% higher than the current system. The TGC hit signals digitized at the frontend electronics are sent to the backend, and muon candidates are reconstructed using the hits. Then, the candidates are combined with information from other detectors to refine transverse momentum (p_T) reconstruction and reduce fake trigger candidates. The precise online estimation of p_T allows us to apply highly efficient trigger condition to select events that contains muons with high p_T. The Sector Logic (SL) is responsible for the online fast reconstruction in the L0 Muon Trigger system, and the algorithms are implemented in a large-scale modern FPGA on the SL. Each step of the reconstruction algorithms is first implemented as individual modules, and all trigger algorithms run sequentially as a chain in a combined firmware. The trigger algorithms are being tested on the prototype trigger board, the SL. The resource usage of the FPGA is reasonable and the trigger latency is within the acceptable limit.

The CoRDIA project aims to develop an X-ray imager capable of continuous operation in excess of 100 kframe/s. The goal is to provide a suitable instrument for Photon Science experiments at diffraction-limited Synchrotron Rings and Free Electron Lasers considering Continuous Wave operation. Several chip prototypes were designed in a 65 nm process: in this paper we will present an overview of the challenges and solutions adopted in the ASIC design.

Accurate clock and time distribution is a key requirement for self-triggered streaming data acquisition in the CBM experiment. This distribution is handled by the Timing and Fast Control (TFC) system by clock forwarding and broadcasting the common time over latency-deterministic optical links in a hierarchical FPGA network. The point-to-point optical connections are served by the latency-optimized GBT-FPGA core, which has been developed at CERN. In the presented work, the performance of GBT-FPGA links for time and clock distribution in a scaled TFC system with multiple hops and endpoints has been investigated.

Silicon PhotoMultipliers (SiPMs) are widely employed for several applications, such as High Energy Physics experiments, as well as other research and industrial fields. SiPMs operating at low temperature, in particular, are the most interesting application for the new large particle detectors for neutrinos and dark matter experiments. In this work we present a low-noise, high-speed front-end electronics (Front-End Boards, FEBs) for large area SiPMs to be employed in the JUNO-TAO experiment for rare event searching. The FEBs are able to manage the signals coming from a 25 cm² SiPM tile, showing single photoelectron resolution better than 13% and dynamic range up to 250 photoelectrons. A careful approach to the front-end electronics design has shown to be critical in order to fully keep the exceptional performances of the SiPMs in terms of single photon detection, dynamic range, and fast timing properties. The sub-nanosecond timing properties make them suitable to work with the typical mixtures of liquid scintillators currently being used in particle and astroparticle physics experiments. The JUNO-TAO detector will achieve an energy resolution better than 2% at 1 MeV by the use of state-of-the-art SiPMs operating at -50°C. A dedicated readout system has been developed in order to collect and digitize the ∼8,000 channels needed to ensure the requested performances. A complete test report about the performance of the pre-production FEBs batch will be presented, showing the solution taken to ensure a high stability and reproducibility of the results.

For the High-Luminosity LHC (HL-LHC) era, the trigger and data acquisition system of the CMS experiment will be entirely replaced. The HL-LHC CMS Level-1 Trigger system will consist of approximately 200 ATCA boards featuring Xilinx UltraScale+ FPGAs connected by 25 Gb/s optical links. These boards will process over 60 Tb/s of detector data within 9.5 μs of the collision to select up to 750 kHz of events for readout. In this paper, we summarise the current status of hardware tests, our progress on system integration tests, and the online software designed to control and monitor these boards.

The assembly of the ATLAS Inner Tracker requires the construction of 19,000 silicon strip sensor detector modules in eight different geometries. Modules will be assembled and tested at 31 institutes on four continents from sensors, readout chips, and flexes. In order to adhere to the module specifications defined for sufficient tracking performance, a rigorous programme of quality control (QC) was established to cover components at every stage of assembly. This contribution presents an overview of the QC programme for ITk strip tracker modules, issues encountered during the pre-production phase (5% of the production volume), and their solutions.

The CMS detector will be upgraded to maintain, or even improve, the physics acceptance under the harsh data taking conditions foreseen during the High-Luminosity LHC operations. In particular, the trigger system (Level-1 and High Level Triggers) will be completely redesigned to utilize detailed information from sub-detectors at the bunch crossing rate: the upgraded Global Trigger will use high-precision trigger objects to provide the Level-1 decision. Besides cut-based algorithms, novel machine-learning-based algorithms will also be included in the Global Trigger to achieve a higher selection efficiency and detect unexpected signals. Implementation of these novel algorithms is presented, focusing on how the neural network models can be optimized to ensure a feasible hardware implementation. The performance and resource usage of the optimized neural network models are discussed in detail.

We present the deployment and testing of an autoencoder trained for unbiased detection of new physics signatures in the CMS Level-1 Global Trigger (GT) test crate during LHC Run 3. The GT test crate is a copy of the main GT system, receiving the same input data, but whose output is not used to trigger the readout of CMS, providing a platform for thorough testing of new trigger algorithms on live data, but without interrupting data taking. We describe the integration of the Neural Network into the GT test crate, and the monitoring, testing, and validation of the algorithm during proton collisions.

In synchrotron light source applications, the photon beam interaction with various materials can produce electric charge which can be measured as current and be used to diagnose particle trajectories, beam intensity, beam profile, position, and stability. Sirius, a 4th-generation Brazilian synchrotron light source, will make use of hundreds of low-intensity measurement instruments. This work aims to show and discuss the design details, challenges, and test results of an Ethernet four-channel high-performance digital ammeter, applied for general-purpose beam diagnostics. The device is based on low-noise and extremely low input bias bipolar transimpedance amplifiers with eight selectable ranges (full scales from pA to mA). Characterization results show that the achieved gain, accuracy, and noise performance are on the same order of magnitude as those of expensive commercial benchtop equipment. In low bandwidth applications, the device was able to measure amplitudes of hundreds of picoampere with intrinsic noise of units of femtoampere (RMS). The designed device is a cost-effective solution.

For optimal operations in the high radiation and pileup environment of the HL-LHC, the CMS-HGCAL requires precise timing information at the level of 30 ps (RMS) for a particle shower. The time measurement in silicon detector modules is performed using a per-channel time-of-arrival discriminator coupled with charge measurement to correct for the time-walk. The module design includes access holes in the PCB and in the sensor passivation to enable infrared laser light to be injected directly into the sensor cells. We present the calibration and timing-in of the system used to perform measurements.

RDMA communication is an efficient choice for many applications, such as data acquisition systems, data center networking and any other networking application, where high bandwidth and low latency are necessary. RDMA can be implemented using a large array of options, which need to be tailored to the needed use case, in order to get optimal results. Aspects such as the effects of using multiple simultaneous connections, using various transport functions such as RDMA Write and RDMA Send and communication models such as sending individual bursts or continuous streams of data will be investigated for implementing RDMA on FPGA devices.

We present the design and performance of the On-Board electronics for the Drift Tubes (OBDT) for the superlayer theta along the direction parallel to the beam-line, the new board built to substitute part of the CMS DT Muon on-detector electronics. The OBDT-theta is responsible for the time digitization of the DT chamber signals for the theta view, allowing further tracking and triggering of the barrel muons. It is also in charge of part of the slow-control of the DT chamber inner electronics in the theta view. Prototypes of the OBDT-theta board are under validation in different laboratories in CERN, as well as in demonstrator chambers installed in the CMS experiment. This allows evaluation of the full functionality of the boards in real conditions, showing very satisfactory results.

The PANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary cluster jet target. The PANDA detector will be composed of several sub-detectors designed for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) is the innermost part of the tracking system surrounding the interaction region, which is designed for precise vertex and tracking detection. It consists of silicon pixel and double-sided microstrip detectors. For the readout of the microstrip sensors an ASIC called ToASt (Torino Asic for Strip readout) is being developed in 0.11 μm CMOS technology at INFN Turin. The ASIC takes advantage of both Time-over-Threshold and Time-of-Arrival methods to accurately measure the event's energy and timestamp. To sustain the acquisition of the microstrip sensors a MDC (Module Data Concentrator) ASIC is under development at KIT. Up to eight ToASt front-ends' data streams are multiplexed, read out and processed by one MDC. The data of several MDCs are collected and processed by the off-detector readout card MMB (MVD Multiplexer Board), also under development at KIT. The processed data is then transferred via 100 GbE optical links to the computing nodes. The ToASt chips have been integrated with the FPGA implementation of the MDC to form the first fully functional detector module. Beam tests have been performed at the COSY facility in Jülich. This paper focuses on the design of MDC ASIC and MMB board, the integration with the ToASt and presents preliminary beam test results.

The MUX64 ASIC is a 64-to-1 analog multiplexer to accommodate 64 inputs, with one addressed to output for ADC readout. It is developed for monitoring of the Low-Gain Avalanche Detectors (LGAD) detector modules in the High Granularity Timing Detector (HGTD) of the ATLAS Phase-II upgrade. The MUX64 chips will be used in the radiation field of high-luminosity pp collisions at LHC to an integrated luminosity of 4000 fb^-1. This work presents the radiation tolerance study for the MUX64 being tested with 80 MeV protons and X-ray exposures for damages caused by Non-Ionizing Energy Loss (NIEL) and Total Ionizing Dose (TID), respectively. The irradiated samples demonstrated tolerance to the NIEL to a fluence of 3.21 × 10¹⁵(Si, 1 MeV) n_eq/cm², and the TID of 7.46 × 10⁵ Gy (Si).

Several physics experiments are moving towards new acquisition models. In this work some ideas to implement Remote Direct Memory Access (RDMA) directly on the front-end electronics have been explored, part of the computing farm's CPU resources could be freed. New simulation techniques are introduced to understand RDMA over Converged Ethernet (RoCE) firmware block developed at ETH Zürich, including real-time firmware simulation leveraging SystemVerilog's useful features. The ability to explore a wider and dynamic inputs increases the likelihood of uncovering potential issues, identifying edge cases, and validating the system's performance across a broader range of scenarios.

The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO₂) with different back-gate bias configurations, from -8 V to 2 V. The investigation revealed that the performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide.

The consolidation of the Large Hadron Collider (LHC) beam position monitor (BPM) requires the deployment of about 5000 single-mode radiation-tolerant optical transmitters, working at 10 Gbps during 20 years of operation. While the use of the custom devices being designed at CERN remains the baseline for the project, 8 commercial of the shelf (COTS) optical transceivers have been evaluated as an alternative. This paper presents the results of the full characterization in radiation of these COTS devices, including cumulative effects and single event effects (SEE), evaluated during both data transmission and reception.

With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad and require low power consumption: < 2.5 mW/sensor-channel per chip. We report on the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype. We present a comparison of single event effect (SEE) cross sections measured for different methods of triple modular redundancy using test results from the ECON-T-P1 full-functionality prototype.

This paper introduces an FPGA-based front-end module emulator developed for the High Granularity Timing Detector (HGTD) within the ATLAS experiment at LHC. The emulator serves as a debugger for the HGTD readout system during the stage when the front-end module is not available. Using a Xilinx-Spartan 7 FPGA, the emulator mimics the behavior of the ASIC utilized in the front-end module. In addition, it shares the same dimensions and connectors as its successor, the real front-end module. This emulator has been effectively employed in the design and testing of the HGTD.

UKRI-MPW0 was developed to further improve the radiation tolerance of HV-CMOS pixel sensors. It implements a novel sensor cross-section that uses backside-only biasing to allow high substrate bias voltages > 600 V. In this contribution, the measured results of irradiated UKRI-MPW0 samples are presented, including their current-to-voltage (I-V) characteristics, depletion depth and pixel performance. The chip is proved to have survived high radiation fluence of 3 × 10¹⁵ n_eq/cm².

The Taishan Antineutrino Observatory (TAO) has been proposed to precisely measure the reactor antineutrino spectrum with an energy resolution better than 2% at 1 MeV. It can provide a reference spectrum to the Jiangmen Underground Neutrino Observatory (JUNO) to enhance its sensitivity to the neutrino mass ordering measurement. In addition, TAO can also provide a benchmark to verify the nuclear database and conduct new physics searches. The TAO detector is a 2.8-ton liquid scintillator detector equipped with a 10 m² silicon photomultiplier (SiPM) array to collect the light with a coverage of 94%. The TAO detector will be operated at -50 °C to suppress the SiPM dark count rate. In this work, we report on the design of a readout system based on the KLauS6 chip to handle the outputs from the SiPMs, which exhibits advantages of high granularity (potentially good particle identification) and large dynamic range. A dedicated mockup system has been built and its performance carefully evaluated both at room and low temperatures, measuring gain, charge linearity, signal-to-noise ratio, and dead time. The testing results show that the performance of this system can meet the requirements of TAO. However, an abnormal increase in current at 1.8 V analog power of the KLauS6 chip has been observed when operating it at temperatures below -20 °C, resulting in a potential risk on the long-term reliability. Therefore, the KLauS-based readout design is considered as an alternative option for the future upgrading of the TAO's readout system. This study also provides a reference and guidance for other relevant applications.

Advances in timing detector technology require new specialized readout electronics. Applications demand below 10 ps time of arrival resolution and low power for a low repetition rate. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc., in collaboration with UC Santa Cruz, has developed a prototype SiGe front-end readout chip optimized for low power and timing resolution. Two versions of the chip were produced with performance in simulation: a more power version with 10 ps resolution at 5 fC with 1.1 mW/channel, and a less power version with 10 ps resolution at 8 fC with 0.6 mW/channel. The chip was produced at Tower Semiconductor with 350 nm technology. The ASIC from the prototype run shows good performance: a rise time of 0.7–1 ns and 25 mV per fC response with RMS noise <1 mV. Simulation and results from the prototype will be reported in this paper.

This work is concerned with the design and the characterization of front-end channels, developed in a 28 nm CMOS technology, conceived for the readout of pixel sensors in future, high-rate applications at the next generation facilities. Two front-end architectures are discussed. In the first one, an in-pixel flash ADC is exploited for the digitization of the signal, whereas the second one features a Time-over-Threshold (ToT) approach. A prototype including the ADC-based front-end has been submitted and the characterization of the chip is discussed in the paper. Simulation results relevant to the ToT-based architecture are reported.

H2GCROC is a 130 nm CMOS ASIC designed to read out the SiPMs coupled to the scintillating tiles of the back hadronic sections of CMS HGCAL. Each of its 72 channels comprises a current conveyor, a high-gain preamplifier, a shaper, an ADC for energy measurement, and two discriminators linked to TDCs for capturing time-of-arrival and time-over-threshold information, respectively. This work presents the ASIC architecture and its characterization in the laboratory and test beam environments. The results demonstrate its adaptability in calibration, proving its capability to measure the SiPM single-photon spectrum and MIP's energy with high resolution under the expected radiation conditions during the entire operation of HGCAL.

Within the project of building a time projection chamber using 100 kg of high-pressure  ⁸⁶SeF₆ gas to search for the neutrinoless double-beta decay in the NvDEx collaboration, we are developing a CMOS charge sensor, named Topmetal-S, which is tailored for the experiment to detect the ions without gas amplification. In this work, the performance of the sensor is presented. The equivalent noise charge of the sensor is measured to be about 120 to 140 e^- depending on the operating point, with the charge injection capacitance calibrated against external capacitors. The signal waveforms are investigated with various chip parameters and experimental settings. In addition to electrons, both negatively and positively charged ions could be detected, and their waveforms are studied using air and SF₆  gases. Using the sensor, the mobility of negative ions in ambient air in the atmospheric pressure is measured to be 1.555 ± 0.038 cm² · V^-1 · s^-1. Our study demonstrates that the Topmetal-S chip could be used as the ion detection charge sensor for the experiment. Further work is ongoing to reduce the noise of the sensor and to develop a small readout plane with tens of the sensors.

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes. The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

The control and data acquisition systems for high energy physics (HEP) applications require a suitable hardware platform to ensure system availability and reliability, so the micro telecommunications computing architecture (MicroTCA) standard is widely utilized in the field of HEP. As a fundamental component of the MicroTCA system, the advanced mezzanine card (AMC) requires efficient module management controller (MMC) to perform board monitoring and management. Therefore, the real-time responsiveness of the module management controller is crucial. Presently, most existing MMC solutions implemented on microcontroller chips with commercial architecture cores such as AVR and ARM. The open-source and customizable RISC-V instruction set architecture has gained widespread attention and adoption due to its advantages such as simplicity, modularity, scalability, low power consumption, and efficiency. In this study, we successfully implemented a MMC solution based on the RISC-V core microcontroller GD32VF103, and evaluated the real-time performance of MMC on both the GD32VF103 and the ARM-based STM32F100 through hot swap response time testing. The results reveal real-time performance of the firmware on the GD32VF103 chip compared to the STM32F100 chip, exhibiting a notable speed improvement of approximately 61.4%. Thus, RISC-V architecture chips exhibit significant potential as MMC solutions within MicroTCA systems.

For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm² can currently not be reached due to the digital consumption of 3.08 mW/cm², while the analog power consumption of 1.04 mW/cm² and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm² is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).

After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the High Luminosity-LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs electro-optical conversion of signals from the pixel modules. This paper presents recent results related to the performance of the data transmission chain with a focus on the Optoboards and to the design, testing and production of the Optopanels.

We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase Locked Loop (PLL) based on a Voltage Controlled Ring Oscillator (VCRO) under a proton beam. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) matrices for the High-Luminosity Large Hadron Collider (HL-LHC). We detail the methodology developed to study such events that could degrade the targeted time resolution of 35 ps per hit. Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. The results are extrapolated to the HL-LHC radiation conditions.

ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC)² shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution. ALFE2 is characterized using a Front-End Test Board (FETB) based on a Zynq UltraScale+ MPSoC and two octal-channel 16-bit high-speed ADCs. The test results indicate that ALFE2 fulfills or greatly exceeds all specifications on gain, noise, linearity, uniformity, and radiation tolerance.

The Belle II collaboration has initiated a program to upgrade its detector in order to address the challenges set by the increase of the SuperKEKB collider luminosity, targeting 6×10³⁵ cm² s^-1. A monolithic CMOS pixel sensor named OBELIX (Optimized BELle II pIXel) is proposed to equip 5 detection layers upgrading the current vertex detector. Based on the existing TJ-Monopix2, OBELIX is currently designed in 180 nm CMOS process.

This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time pick-off and a Time-to-Digital Converter (TDC) for digitization.

The ECAL Barrel and MTD Barrel Timing Layer subdetectors of CMS are approaching series production of electronic boards, including voltage conditioning PCBs: LVRs and PCCs respectively. 2448 LVRs and 864 PCCs will be installed during LS3 of the LHC. These boards are hosting radiation-tolerant bPOL12V ASICs which convert a broad input voltage range into required voltage levels for microelectronics between 1.2–2.5 V. Each card must be tested multiple times at various production stages to ensure its conformity. This contribution describes a methodology of testing bPOL12V conversion quality including the detection of instability regions at certain load levels.

NAPA-p1 is a prototype Monolithic Active Pixel Sensor 'MAPS' developed as a first iteration towards meeting the detectors general requirements for future e⁺e^- colliders. Long-term objective is to develop a wafer-scale sensor in MAPS with an area ∼ 10 cm × 10 cm. This article presents the motivations for the design choices of NAPA-p1, translating the physics requirement into circuit specifications. Simulations show a pixel jitter of < 400 ps-rms and an equivalent noise charge of 13 e^-rms with an average power consumption of 1.15 mW/cm² assuming a 1% duty cycle, meeting the target specifications. The prototype is designed in 65 nm CMOS imaging technology, with dimensions of 1.5 mm × 1.5 mm and a pixel pitch of 25 μm. The prototype chip has been fabricated and characterization results will be available soon.

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. The second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.

The design of HVCMOS detectors for measuring Galactic Cosmic Rays (GCR) and Solar Energetic Particles (SEP) is presented, with the goal of covering a very wide dynamic range (from ∼0.5 fC to pC). Two different pixel designs are shown, one with low gain tailored to high energy depositions and one with high gain for low energy depositions. Both designs utilize a sensing diode consisting of a fully-depleted, high resistivity substrate and a segmented deep n-well on top. LFoundry 0.15 μm technology is used. The design choices are backed by simulation results and preliminary measurements.

The Phase-2 Upgrade [1] of the CMS Outer Tracker [2] requires the production of 7608 Strip-Strip (2S) and 5592 Pixel-Strip (PS) modules, altogether incorporating 45 192 hybrid circuits of 15 design variants. The module design makes the potential repairs impractical; therefore, performing production-scale testing of the hybrids is essential. Accordingly, a scalable, crate-based test system was designed and manufactured, allowing for parallel, high-throughput testing. To reproduce the operating conditions, the system was integrated within a climate chamber, which required the development of a remote control interface and the calibration of thermal cycles. The results and lessons learned from the test system integration and commissioning will be presented.

MightyPix is a high voltage complementary metal-oxide-semiconductor (HV-CMOS) active pixel sensor, currently being developed for the Mighty Tracker, an upgrade proposed for LHCb in anticipation of the High Luminosity LHC. To ensure that MightyPix will be able to handle the particle hit rates at the Mighty Tracker, which are expected to reach 17 MHz/cm², simulations of the chip's digital readout mechanism were performed. Using simulated particle hits the chip's performance within the LHCb environment is characterised. For this, a behavioural model of the first prototype, MightyPix1, representing the analogue pixel matrix, together with the synthesised digital logic is used. Simulation results show the MightyPix1 readout mechanism having an efficiency over 99 % up to 20 MHz/cm². The bottleneck was found to be the speed at which the hits are read out. This yielded new design ideas to improve the readout for MightyPix2, leading to an efficiency of over 99 % up to 30 MHz/cm².

The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. Around 200,000 chips have been tested with a production test system capable of exercising the majority of the ASIC functionality to ensure its correct operation. Furthermore, specific individual qualification tests were carried out beyond the production tester limits, including radiation, multi-drop bus topology, inter-chip communication through different types of electrical links and characterization of jitter and stability of the recovered clocks. In this article, an overview of the production and qualification tests is given together with their results demonstrating the robustness and flexibility of the lpGBT.

During the next Long Shutdown (LS3) of the LHC, planned for 2026, the innermost three layers of the ALICE Inner Tracking System will be replaced by a new vertex detector composed of curved ultra-thin monolithic silicon sensors. The R&D initiative on monolithic sensors of the CERN Experimental Physics Department, in cooperation with the ALICE ITS3 upgrade project, prepared the first submission of chip designs in the TPSCo 65 nm technology, called MLR1 (Multi Layer Reticle). It contains four different test structures with different process splits and pixel designs. These proceedings illustrate the first validation of the technology in terms of pixel performance and radiation hardness.

The ALICE Collaboration will replace the three innermost layers of the Inner Tracker System (ITS) at the LHC with an innovative vertex detector. A single-die stitched monolithic pixel detector segment of 1.85 cm × 26.6 cm designed in 65 nm CMOS imaging technology will be used as a building block for these layers. The pixel detector segment consists of 144 data transmitters that are evenly distributed over the full area. The data communication is done via the 1.85 cm short edge of the detector. This contribution will focus on the architecture, challenges, and techniques used to aggregate up to 30.72 Gb/s of data flux arriving at the short edge of the chip and to send it off-chip.

The construction of the ATLAS strip tracker barrel will require the assembly of 12,000 barrel detector modules over the course of 3.5 years. In 2022, during the module pre-production phase, modules were found to display clusters of noisy channels outside required specifications when tested at operating temperatures (-35°C), called "Cold Noise". Extensive investigations into the cause and mechanism of Cold Noise interrupted pre-production and occupied most barrel module assembly sites. This contribution presents an overview of the year-long investigations into Cold Noise, the final identification of the underlying mechanism and necessary changes for the transition to production.

We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.

The ITS3 upgrade baseline design employs MAPS (Monolithic Active Pixel Sensor) in bent state. Bending experiments with the existing ITS2 MAPS (=Alpide chip) show it remains functional but with relative large analog supply current changes. It is shown that by the piezoresistive effect, rotation of current mirror FETs can be responsible which was confirmed after validating the layout. Measured Gauge Factor has proper sign but is 3 times lower than typical values derived from literature. The magnitude of the measured strain induced PMOS V_th shift is as expected but the sign differs for compressive strain with some of the literature.

The CMS Tracker Phase-2 Upgrade requires the production of new sensor modules to cope with the requirements of the HL-LHC. The two main building blocks of the Outer Tracker are the Strip-Strip and Pixel-Strip modules. All-together 47'520 hybrid circuits will be produced to construct 8'000 Strip-Strip and 5'880 Pixel-Strip modules. The circuit designs for the mass production were fine-tuned and kick-off batches were manufactured to verify the latest changes in the designs before the series production. This contribution focuses on lessons learned from the prototyping stage, design optimization details for the mass production as well as test results and production yield from the kick-off batches.

The extremely low dark current of silicon carbide (SiC) detectors, even after high-fluence irradiation, was utilized to develop a beam monitoring system for a wide range of particle rates, i.e., from the kHz to the GHz regime. The system is completely built from off-the-shelf components and is focused on compactness and simple deployment. Beam tests using a 50 um thick SiC detector reveal, that for low fluences, single particles can be detected and counted. For higher fluences, beam properties were extracted from beam cross sections using a silicon strip detector. Overall, accurate results were achieved up to a particle rate of 10⁹ particles per second.

A series of monolithic High Voltage CMOS (HV-CMOS) pixel sensor prototypes have been developed by the CERN-RD50 CMOS working group for potential use in future high luminosity experiments. The aim is to further improve the performance of HV-CMOS sensors, especially in terms of pixel granularity, timing resolution and radiation tolerance. The evaluation of one of this series, RD50-MPW3, is presented in this contribution, including laboratory and test beam measurements. The design of the latest prototype, RD50-MPW4, which resolves issues found in RD50-MPW3 and implements further improvements, is described.

We report on the development and performance of a digitally controlled phase delay with a step of 280 femtoseconds and a dynamic range of 230 picoseconds. Details of the device design and the simulations as well as comparisons with laboratory measurements will be discussed. We describe how we have used this ASIC to stabilize a digital clock to a precision of less than one picosecond.

The LHC upgrade requires redoing the liquid Argon (LAr) calibration system which should provide a 16-bit range signal with 1‰ accuracy while being radiation tolerant. The fundamental operating principle remains unchanged: a precise current is stored in an inductor, and upon switching off the current, a pulse is generated for injection into the readout electronics. This is achieved by two chips: the first one, in CMOS 130 nm, provides the 16-bit DAC as well as the calibration management system; the second one, in XFAB 180 nm, embeds switches to generate the pulses. A description of both chips and measurement results will be presented.

For the Phase-II upgrade of the ATLAS Muon Spectrometer to High-Luminosity LHC, new front-end readout electronics for the Monitored Drift Tube chambers is required, as the old one no longer meets the demands. The first stage in the Monitored Drift Tubes readout chain is the Amplifier-Shaper-Discriminator chip. For the upgrade, the new ASD2 ASIC chip in IBM 130 nm CMOS technology has been developed. For the ATLAS experiment, 80000 ASD2 chips are produced, which have to be tested before integration in order to obtain the required 50000 well-performing chips in the end. Using a prototype tester board and pre-production ASD2 chips, the overall performance and the influence on programmable parameters is investigated. Based on these results, 1775 production chips are tested to define final optimized cut values for the automated production testing of all chips in the company.

The LHCb collaboration proposes a Phase-II Upgrade of the detector, to be installed during the LHC Long Shutdown 4 (2032–2034). Operating in the HL-LHC environment poses significant challenges to the design of the upgraded detector, and in particular to its tracking system. The primary and secondary vertices reconstruction will become more difficult due to the increase, by a factor of 7.5, of the average number of interactions per bunch crossing. The performance of the VErtex LOcator (VELO), which is the tracking detector surrounding the interaction region, is essential to the success of this Phase-II Upgrade. Data rates are especially critical for the LHCb full software trigger, and with the expected higher particle flux, the VELO Upgrade-II detector will have to tolerate a dramatically increased data rate: assuming the same hybrid pixel design and detector geometry, the front-end electronics (ASICs) of the VELO Upgrade-II will have to cope with rates as high as 8 Ghits/s, with the hottest pixels reaching up to 500 khits/s. With this input rate, the data output from the VELO will exceed 30 Tbit/s, with potentially a further increase if more information is added to the read-out. This paper outlines the challenges being addressed and the solutions under investigation for reading out the VELO sub-detector.

For the high-luminosity upgrade of the ATLAS Inner Tracking detector of the ATLAS experiment, a new pixel detector will be installed to allow for a bigger bandwidth and cope with the increased radiation among other challenges. This contribution will present the evaluation of the Outer Barrel Pixel layer services chains. A full data transmission study covering data merging will be presented from the pixel module all the way to the FELIX data acquisition system, using most of the components foreseen for the detector. Challenges and results of the services chain of the Outer Barrel will be highlighted.

This contribution describes the characterisation and validation campaign of the prototype of the CMS Readout Chip (CROC), a 65 nm CMOS pixel readout ASIC for the CMS Inner Tracker upgrade for High Luminosity LHC. This validation campaign includes tests with single-chip and multi-chip modules, irradiation campaigns, test beams and wafer-level tests. The main results obtained in the testing of the CROC prototype will be outlined. Key improvements and fixes that have been implemented in the final version of the chip before the October 2023 submission will be described.

An initial characterization of the BigRock high-speed, low-power Analog Front End (AFE) is presented. The BigRock AFE previously described in [1] has been refined in a second generation testbed ASIC, Pebbles. The AFE utilizes a current-mode signal path that has been designed for 4D tracking applications with precision time resolution of order 50 ps. The preamplifier concept is based on a prior art current-feedback CMOS topology in [2]. An on-chip test bench comprised of a variable injection circuit and high-resolution TDC measures the AFE timing resolution. An array of integrated load capacitors and IO IPs enhance the characterization capability. These full-custom pads include LVDS and clock receivers, CML output driver, and simple analog buffer pads designed at the process core voltage (0.9 V) on a 90 μm/180 μm pitch. Critical noise and timing metrics for an array of input detector capacitance ranging 0 to 100 fF have been measured.

We present in this paper a new sensor called PICMIC-0 that is intended to exploit the intrinsic spatial resolution of the MicroChannel Plate (MCP) detectors. Manufactured using 6-metal TowerJazz 180 nm wafer technology, the sensor features hexagonal charge collection pixels on the top metal layer with a pitch of 5 μm and covering an area of 7.4 × 6.4 mm². The 2 million of the pixels of this sensor are not read out individually. Each pixel is connected to a straight-line in either 0°, 120° or -120° orientation, in which a current is produced in case of a hit. Each of these readout strip-lines is connected to a readout cell which receives this current, amplifies it using a current mirror and converts it into a digital signal by means of a current comparator. The data is collected from the digital outputs of the readout cells using a priority encoder readout scheme and transmitted in frames of 400 ns. This projective readout system reduces the number of channels to be read out from 2 million pixels to 2556 readout cells integrated within the pixel matrix. Using three projections reduces the ambiguity in case of multiple hits.

A novel Data Acquisition (DAQ) system, known as Level-1 Data Scouting (L1DS), is being introduced as part of the Level-1 (L1) trigger of the CMS experiment. The L1DS system will receive the L1 intermediate primitives from the CMS Phase-2 L1 trigger on the DAQ-800 custom boards, designed for the Phase-2 central DAQ. Firmware is being developed for this purpose on the Xilinx VCU128 board, with features similar to one half of the DAQ-800, and validated in a demonstrator for LHC Run-3. This contribution describes the firmware development in view of the target design for the DAQ-800.

The paper describes a new figure of merit reachable in terms of very low power dissipation for a 12 bit, 40 MS/s Analog to Digital Converter in a 65 nm CMOS process with 1 V power supply. A differential time interleaved successive approximations register architecture is used. Each individual ADC channel is optimized with regard to power consumption hence interleaving 28 ADC channels in an analog memory like method, the total power consumption is only 280 μW including all the reference voltage drivers, the clock management and the digital sections. The total layout area of this converter is 0.87 mm².

This paper presents the design and measurement results of a 768-channel of a 14-bit analog to digital converters. Each sampling channel is equivalent to a pitch of only 8.5 μm with a possible sampling rate from 40 KS/s up to 100 KS/s. Test results show crosstalk of just ⁺/_-1 LSB. The circuit architecture and layout structure make it scalable to an exceptionally large format of detectors beyond 1000 channels. The circuit is designed to be used as a side element for multi-channel readout systems or as an IP for transfer to very dense integrated circuits.

Maintaining the required performance of the CMS electromagnetic calorimeter (ECAL) barrel at the High-Luminosity Large Hadron Collider (HL-LHC) requires the replacement of the entire on-detector electronics. 12240 new very front end (VFE) cards will amplify and digitize the signals of 61200 lead-tungstate crystals instrumented with avalanche photodiodes. The VFE cards host five channels of CATIA pre-amplifier ASICs followed by LiTE-DTU ASICs, which digitize signals with 160 MS/s and 12bit resolution. We present the strategy and infrastructure developed for achieving the required reliability of less than 0.5% failing channels over the expected lifetime of 20 years. This includes the choice of standards, design for reliability and manufacturing, as well as factory acceptance tests, reception testing, environmental stress screening and calibration of the VFE cards.

The Jiangmen Underground Neutrino Observatory (JUNO) aims to determine the neutrino mass hierarchy by detecting antineutrinos from nuclear reactors using a large liquid scintillator volume. The detector employs approximately 20,000 20-inch photomultiplier tubes powered and read out by two electronics readout systems: underwater and above water. The back-end card (BEC) is a crucial component of the latter and links 7,000 underwater electronics boxes to the trigger system. 180 BECs have been installed and tested at the JUNO site, including self-tests and combined tests. This paper presents the current status of the BEC.

Single-event effects and hardware security show close similarities in terms of vulnerabilities and mitigation techniques. Secure processors address physical attacks from the outside, such as external laser stimulation, to compromise the program and extract sensitive information from the systems. To overcome this vulnerability, secure extensions to the hardware architecture are often built into modern processor cores. Given the limited design resources often found in space or high-energy physics experiment development teams, this article addresses the extent to which secure hardware architectures can be a reliable source of processor SEU detection.

The MDT Trigger Processor (MDTTP) is a key ATLAS Level-0 Muon trigger upgrade component designed to meet High-Luminosity LHC requirements. The MDTTP will use MDT hits in the hardware level trigger for the first time in ATLAS to improve the momentum resolution of muon candidates provided by RPC and TGC detectors and reduce the fake muon trigger rate. The MDTTP hardware is based on the Apollo ATCA platform. The prototype includes a VU13P-FPGA, high-speed FireFly optical transceivers, peripherals, and other improvements learned from using the previous hardware demonstrator. We present the prototype status, firmware implementation, core algorithm, slow-control software, and first integration tests.

We present the recent development of a lightweight detector capable of accurate spatial, timing, and amplitude resolution of charged particles. The technology is based on double-sided double-metal p+ – n – n+ micro-strip silicon sensors, ultra-light long aluminum-polyimide micro-cables for the analogue signal transfer, and a custom-developed SMX read-out ASIC capable of measurement of the time (Δt ≲ 5 ns) and amplitude. Dense detector integration enables a material budget > 0.3 % X₀. A sophisticated powering and grounding scheme keeps the noise under control. In addition to its primary application in Silicon Tracking System of the future CBM experiment in Darmstadt, our detector will be utilized in other research applications.