Adarsha Rao

I’m thrilled to announce that my paper, “Averting Hacks of PCIe Transport using CMA/SPDM,” has been published! 🚀 In this paper, I dive into how secure connections are built to protect data, using symmetric and asymmetric flows. I also discuss how next-gen ICVIP systems are evolving to verify SPDM software for tighter security 🔐. We break down how Diffie-Hellman Key Exchange (DHE) 🔑 generates secure keys and how the Digital Signature Algorithm (DSA) ✍️ is used to authenticate data through digital signatures. The real game-changer? Elliptical curve cryptography 🧠! It's not only faster but also way more efficient than traditional methods for establishing secure connections. 🚀 I’d love for you to check it out here and share any valuable feedback or insights! #PCIe #SIEMENS #Cybersecurity #Encryption #CMA #SPDM #EllipticalCurveCryptography #DHE #DSA #ICVIP #NextGenTech #SecureConnections #TechInnovation

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My article on SuperComputing Architecture Shift in EFY's Aug Magazine. "The silicon chipset, which is procured from Intel as of today, is the most crucial component in the high-performance compute server. Everything involved in making a supercomputer like the motherboard, the rack, cooling systems, and the software stack, depends on the architecture and features of the silicon chipset. " Electronics For You #Aum #Supercomputing #HPC

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https://lnkd.in/daVQFJuc the fact that Amazon Web Services (AWS) and Amazon can pause orders of NVIDIA chips points to the fact that a hoge amount of the demand for #AI training chips is essentially hoarding by datacenter companies if they could deploy the #GraceHopper chips immediately #Amazon would never hit pause Amazon is hitting pause not only because it wants to wait for Blackwell, but likely mainly because it doesn't know how to recover money spent on it's existing #AI cloud infrastructure this is probably not good news for Nvidia and other #AI training chips companies that doesn't mean it is bad for #AI though, focus will shift to applications and inference and everyone will benefit. Also companies like Lattice Semiconductor focusing mainly on inference will tend to become more popular

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Is Intel Corporation the new Kodak? Over the past decades, Intel has missed significant opportunities in the processor market, particularly for smartphones and tablets. Today, it holds a minimal role in AI and is losing ground in data centers. Intel also lost Apple’s MAC computer business. Recently, a new trend has emerged with AI-enabled laptops using Qualcomm and NVIDIA setups. What’s left for Intel? Is its future as a pure foundry? Can it catch up with likes of TSMC and Samsung Semiconductor? Or will it resurface as a major player in any of the processor sectors? #AI #Semiconductor #Smartphone #Datacenter #Kodak #processor

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AI everywhere, how can silicon be left behind !!! VLSID 2025 bring you - Silicon Meets AI: Sustainable innovations in Accelerated Computing, Secure Connectivity and Intelligent Mobility Call for Papers open. Submit yours now!

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🏏 Just like winning a nail-biting IPL match, deciding between component-level and Next Higher Assembly (NHA) Last Time Buys (LTBs) in semiconductor manufacturing demands strategic finesse and a sharp eye for value! 💡 . . . 🔍 Problem: It's like being at a crucial crossroads—I've experienced the dilemma firsthand, torn between securing individual parts or opting for pre-assembled units. #Semiconductors 💡 From my learning in the Semiconductor industry, I follow the following strategies to solve the problem: 1️⃣ Evaluate Supply Chain Reliability: Trust me, assessing supplier reliability is key—just like scouting for dependable players. 🔍 2️⃣ Analyze Cost Implications: Carefully weigh costs, like managing a team budget. Investing upfront in NHAs can pay off in the long run. 💰 3️⃣ Track Technological Lifecycles: Stay ahead of tech trends, like picking promising young talent. Opt for components or NHAs with longevity to stay competitive. 🔄 #Innovation 4️⃣ Forecast Demand Accurately: Anticipating market demand is crucial, similar to predicting match outcomes. Stay agile and responsive to market shifts. 📈 5️⃣ Assess Assembly Complexity: Know your assembly process well, like understanding your team's playing style. Simplifying leads to smoother operations. 🛠️" With the right LTB strategy, victory isn't just a dream—it's within reach. 🏆 Like winning an IPL match, streamlined operations, minimized risks, and optimized performance await. 🚀 Care to share your valuable thoughts on this topic? 💬 #SupplyChain #Sustainability #AI Picture source: Telegraph

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#AI and high performance computing demands have revolutionized the silicon, leading to a race to create the most massive and fastest designs achievable. At Baya Systems, we are witnessing the emergence of multi PB/s bi-section bandwidth within package, surpassing wire bandwidth growth physics. Outdated legacy communication solutions result in excessive power and area (x++% power, area for x% perf gain). This is unsustainable and calls for a transformation in on- and inter-chiplet communication and optimization strategies. In the race of high performance computing and AI silicon development, prioritizing #chiplet and on-chip communication for multi PB/s bandwidth is not only critical to win but just to stay in the game. Check out the link for more insights: [https://lnkd.in/g6cGtrH9]

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Class B amplifiers are sometimes OK for RF but not audio. Why? 👇🏽 Class B amplifiers provide a highly distorted output signal, but with good amplification efficiency. For many RF applications, it is okay to distort the carrier signal as long as the modulation is not affected. The baseband information can still be retrieved. Class B won't work for audio. It is a complex time-varying signal which needs to be accurately amplified. To still get Class B efficiencies, the push-pull amplifier was invented. It is a differential version of a Class B amplifier that can produce amplification with good efficiency. If you'd like to learn more about Class B and push-pull amplifiers, stay tuned for this week's newsletter. ✍🏼 Sign up here: www.viksnewsletter.com What is your experience with Class B or audio? Let me know! ~~ 🔔 Follow me for posts on RF engineering ♻️ Repost if you found it useful.

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Unraveling the Newly Introduced Segmentation in PCIe 6.0 ======================================= Segment numbers embedded in PCIe 6.0 FLIT headers offload peer-to-peer traffic management from the Root Complex, enabling smarter switch routing for efficient data flow and reduced system complexity and cost. Explore more details in below article.. #PCIe6.0

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When creating with MCX and NXP Sensors at my bench… the need for food is subordinate to my need to create…. But then… Tacos.

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𝑾𝒉𝒚 𝑺𝑻𝑴32 𝒆𝒗𝒂𝒍𝒖𝒂𝒕𝒊𝒐𝒏 𝒃𝒐𝒂𝒓𝒅 ?  I have a range of evaluation boards from all well known semiconductor companies including NxP , ST, Nuvoton, TI , Microchip, Broadcom, Nordic, NVIDIA etc. That was part of my investment. I got loaner boards from ST, NxP and Nuvoton. I used following parameters to decide evaluation board : 1: 𝘾𝙤𝙢𝙥𝙖𝙣𝙮 𝙝𝙞𝙨𝙩𝙤𝙧𝙮 I have used ST devices around 1998 as well. 2: 𝙍𝙤𝙖𝙙𝙢𝙖𝙥 : They have a range of products in various domains 3: 𝘾𝙤𝙨𝙩: It is most important factor and their boards are available in Arduino range as well. 4: 𝙀𝙘𝙤𝙨𝙮𝙨𝙩𝙚𝙢 : They have a variety of tools for Pin multiplexing, Flash programming, Debugging and even for AI. 5: 𝙎𝙪𝙥𝙥𝙤𝙧𝙩 :  I never had issue in contacting ST Marketing , Development , FAE and distributor FAEs . In fact , now my student is also supporting ST devices in India. I was invited for a combined session with faculty as well. 6: 𝙅𝙤𝙗 𝙤𝙥𝙥𝙤𝙧𝙩𝙪𝙣𝙞𝙩𝙞𝙚𝙨 : Since STM32 is based on ARM and being widely used in India. It increases your possibility to get job. Here is outcome of my experience with ST device. This week was little bit interesting in embedded system live sessions. 1: Enabled one US based student in the STM32 evaluation board which I never used. It was done in live session. We supported multiple devices in past but it was instant support over live session. 2: Yesterday also another US based student shared board over camera. We started with default HAL project to do sanity check. First surprise was warning " Obsolete board" . We ignored and continued . Next surprise was "Insufficient flash memory" even with default configuration. This was because it had enabled all peripherals. I asked student to put while(1); in the beginning. Linker was kind enough to discard all other code and we could reach at main() at least. This was simple but important for student to move ahead. Both above students are working professionals in US and joined Embedkari for a refresh cycle. For joining Embedkari, no shubh muhurt is required because every moment is part of God's creation 😀 ... Join anytime . and #salarybadhao #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #firmwarejobs #devicedriver #softwareengineers #electronics #embeddedjobs #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers #stm32

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AI Driven Test Space Optimization (TSO.ai) at Synopsys: how to address test challenges with test costs and design schedules.

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Detailed review of Xeon 6 (Granite Rapids). Summary from the conclusion: "Intel has finally solved its core count issue, while also offering things like AMX, QAT, and more for acceleration, high-end DDR5 and MRDIMM (MCR DIMM) solutions for big memory bandwidth, and more. Intel lost its top-end edge when it lost process leadership with 10nm and Ice Lake. As the manufacturing and packaging side has improved, Intel is back in the fight. Welcome back Intel." #intelxeon https://lnkd.in/g-CfuTRj

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Quote: Using the whisper-medium model, an Altra Max M128-30 can do 375,415 transactions per second (TPS), and an Nvidia “Hopper” H100 GPU can do 395,500 TPS. If you cap the racks at 15 kilowatts – which is reasonable in an enterprise datacenter – then 2,400 servers using the Altra Max CPUs in 60 racks costs $17.2 million and delivers 901 million TPS. That works out to a price/performance of $18,979 per million TPS. At the same 60 racks of space at 15 kilowatts per rack, that is only one DGX H100 per rack, which ain’t that much. Those 60 DGX H100s would cost $27.3 million and deliver only 190 million TPS, but cost $143,684 per million TPS. The CPU inference has 7.6X better price/performance on Whisper. You can put four DGXs in each rack and buy 240 of them, for a total of $109.2 million, and drive 760 million TPS, but the price/performance doesn’t change. We suspect the Whisper model is using FP16 half precision data formats and processing, and by moving to FP8, Nvidia could cut that gap in half. But half the gaps is still a 3.8X difference in bang for the buck in favor of the Ampere Computing Arm CPU. https://lnkd.in/gSZcFnm3

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📢 Exciting News! 📢 Our latest research paper, titled "Enhancing Defect Detection in Circuit Board Assembly Using AI and Text Analytics for Component Failure Classification," has been accepted for publication in the IEEE Transactions on Components, Packaging and Manufacturing Technology! 🎉 In this study, we explore how text analytics and AI can revolutionize defect detection in electronics manufacturing by turning unstructured textual data into actionable insights. The findings highlight significant advancements in quality control strategies for circuit board assembly. 🛠️💻 A special thanks to Prof. Edwin Chong, Fellow, IEEE, Department Chair of Electrical & Computer Engineering Department - Colorado State University, and Prof. Steve Simske, Fellow, IEEE, Professor in the CSU Systems Engineering Department —both from Colorado State University, Fort Collins, CO, USA—for their invaluable collaboration and guidance throughout this research. 🙏🎓 🔗 Access the paper here for an early look at our work. https://lnkd.in/e8Rc_ysH #AI #TextAnalytics #ElectronicsManufacturing #CircuitBoard #DefectDetection #IEEE #Research #Engineering #QualityControl #Collaboration #ColoradoStateUniversity

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#HBM3 memory by the nature of its interposer based interconnect sits very close to CPU/GPU in the package as a result memory is usually already close to a die which often runs about 100deg C in temperature. cooling the HBM stack itself becomes very tricky for that reason alone on top of that the HBM memory itself has 8 to 12 DRAM chips in stack on top of a logic die, thermal paths are longer and stacked on top of each other no wonder Samsung Semiconductor is having trouble with it's memory chips in NVIDIA high performance systems this is a classic case of #chiplet based systems-in-package problems https://lnkd.in/gH_D7_tB

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a very comprehensive intro document about Arm CPU architecture another resource is here: https://lnkd.in/gpq5zgWa

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Happy Morning Today Post is Physical Design Inputs: => PD inputs are : netlist, sdc, lef, lib and captables, cpf/upf. • Netlist : It contains the logical connectivity of the design. It contains Hierarchy information , module info , input and output pins info , wire info, instance info. • SDC : It contains clock definitions , input and output delays , DRV’S and path exceptions. • LEF : There are two types of lef’s. 1. Technology lef 2. Cell lef. Technology lef contains physical information of all metal layers in the design. Cell lef contains physical information of the cells. • LIB : It contains PVT information , power information (leakage and internal/short circuit power) , cell functionality and cell timing information. • Captables : It contains resistance and capacitance values for the metal layers based on different width and spacing and different capacitors ( coupling capacitance , fringe capacitance etc) • CPF (Common power format): It contains power domain creation , operating conditions of the domains , low power cell (isolation , level shifter, switch cell, retension flop , always on buffer) rules. #vlsi #semiconductor #physicaldesign #hardware Intel Corporation, Qualcomm, AMD, NVIDIA, Texas Instruments, Samsung Electronics, Synopsys Inc, Cadence Design Systems, Micron Technology, Microchip Technology Inc., NXP Semiconductors, , MediaTek

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