342 Open source projects that are alternatives of or similar to Ivtest

FuseSoC standard core library

冯爱民老师《计算机组成原理A》课程设计

CDBUS Protocol and the IP Core for FPGA users

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

Stuff from CTF contests

FPGA-based RISC-V CPU+SoC.

實作《自己動手寫CPU》書上的程式碼

Code generation tool for configuration and status registers

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Human Resource Machine - CPU Design #HRM

FPGA-based C64 Accelerator / C65 like computer

My solutions to Alteras example labs

High throughput JPEG decoder in Verilog for FPGA

Featherweight RISC-V implementation

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

Realtime VGA to ASCII Art converter

This is the main repository for all the examples for the book Practical UVM

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

The Antikernel operating system project

Haskell to VHDL/Verilog/SystemVerilog compiler

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

RTL, Cmodel, and testbench for NVDLA

Homotopy theory in Coq.

Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)

Example designs showing different ways to use SymbiFlow toolchains.

Mega CD for MiSTer

Bitcoin miner for Xilinx FPGAs

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

A reimplementation of a tiny stack CPU

This is the base project for the Mojo. It should be used as the starting point for all projects.

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

A MIPS CPU implemented in Verilog

A nicer HDL.

CoreIR Symbolic Analyzer

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

This is a higan/Verilator co-simulation example/framework

Verilog and MIPS simple programs

FPGA 101 - Workshop materials

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

A single-wire bi-directional chip-to-chip interface for FPGAs

Image Processing Toolbox in Verilog using Basys3 FPGA

A mixed signal netlist language (pre-alpha)

❄️ Visual editor for open FPGA boards

Sega Genesis for MiSTer

A small 6502 system with MS BASIC in ROM

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

IC design and development should be faster，simpler and more reliable

A very primitive but hopefully self-educational CPU in Verilog

This repository is used to release the Labs of Computer Architecture Course from USTC

A wishbone controlled scope for FPGA's