Revert 9.5 pgindent changes to atomics directory files

This is because there are many __asm__ blocks there that pgindent messes
up.  Also configure pgindent to skip that directory in the future.

Author: bmomjian

src/include/port/atomics/arch-ia64.h

@@ -18,9 +18,9 @@
  * fence.
  */
 #if defined(__INTEL_COMPILER)
-#define pg_memory_barrier_impl()	 __mf()
+#	define pg_memory_barrier_impl()		__mf()
 #elif defined(__GNUC__)
-#define pg_memory_barrier_impl()	 __asm__ __volatile__ ("mf" : : : "memory")
+#	define pg_memory_barrier_impl()		__asm__ __volatile__ ("mf" : : : "memory")
 #elif defined(__hpux)
-#define pg_memory_barrier_impl()	 _Asm_mf()
+#	define pg_memory_barrier_impl()		_Asm_mf()
 #endif

src/include/port/atomics/arch-x86.h

@@ -78,10 +78,9 @@ typedef struct pg_atomic_uint64
 } pg_atomic_uint64;
 #endif
 
-#endif   /* defined(HAVE_ATOMICS) */
+#endif /* defined(HAVE_ATOMICS) */
 
-#endif   /* defined(__GNUC__) &&
-								 * !defined(__INTEL_COMPILER) */
+#endif /* defined(__GNUC__) && !defined(__INTEL_COMPILER) */
 
 #if defined(PG_USE_INLINE) || defined(ATOMICS_INCLUDE_DEFINITIONS)
 
@@ -94,20 +93,20 @@ typedef struct pg_atomic_uint64
  * PAUSE in the inner loop of a spin lock is necessary for good
  * performance:
  *
- *	   The PAUSE instruction improves the performance of IA-32
- *	   processors supporting Hyper-Threading Technology when
- *	   executing spin-wait loops and other routines where one
- *	   thread is accessing a shared lock or semaphore in a tight
- *	   polling loop. When executing a spin-wait loop, the
- *	   processor can suffer a severe performance penalty when
- *	   exiting the loop because it detects a possible memory order
- *	   violation and flushes the core processor's pipeline. The
- *	   PAUSE instruction provides a hint to the processor that the
- *	   code sequence is a spin-wait loop. The processor uses this
- *	   hint to avoid the memory order violation and prevent the
- *	   pipeline flush. In addition, the PAUSE instruction
- *	   de-pipelines the spin-wait loop to prevent it from
- *	   consuming execution resources excessively.
+ *     The PAUSE instruction improves the performance of IA-32
+ *     processors supporting Hyper-Threading Technology when
+ *     executing spin-wait loops and other routines where one
+ *     thread is accessing a shared lock or semaphore in a tight
+ *     polling loop. When executing a spin-wait loop, the
+ *     processor can suffer a severe performance penalty when
+ *     exiting the loop because it detects a possible memory order
+ *     violation and flushes the core processor's pipeline. The
+ *     PAUSE instruction provides a hint to the processor that the
+ *     code sequence is a spin-wait loop. The processor uses this
+ *     hint to avoid the memory order violation and prevent the
+ *     pipeline flush. In addition, the PAUSE instruction
+ *     de-pipelines the spin-wait loop to prevent it from
+ *     consuming execution resources excessively.
  */
 #if defined(__INTEL_COMPILER)
 #define PG_HAVE_SPIN_DELAY
@@ -121,8 +120,8 @@ pg_spin_delay_impl(void)
 static __inline__ void
 pg_spin_delay_impl(void)
 {
-	__asm__		__volatile__(
-										 " rep; nop			\n");
+	__asm__ __volatile__(
+		" rep; nop			\n");
 }
 #elif defined(WIN32_ONLY_COMPILER) && defined(__x86_64__)
 #define PG_HAVE_SPIN_DELAY
@@ -137,10 +136,10 @@ static __forceinline void
 pg_spin_delay_impl(void)
 {
 	/* See comment for gcc code. Same code, MASM syntax */
-	__asm rep	nop;
+	__asm rep nop;
 }
 #endif
-#endif   /* !defined(PG_HAVE_SPIN_DELAY) */
+#endif /* !defined(PG_HAVE_SPIN_DELAY) */
 
 
 #if defined(HAVE_ATOMICS)
@@ -154,13 +153,12 @@ pg_atomic_test_set_flag_impl(volatile pg_atomic_flag *ptr)
 {
 	register char _res = 1;
 
-	__asm__		__volatile__(
-										 "	lock			\n"
-										 "	xchgb	%0,%1	\n"
-							 :			 "+q"(_res), "+m"(ptr->value)
-							 :
-							 :			 "memory");
-
+	__asm__ __volatile__(
+		"	lock			\n"
+		"	xchgb	%0,%1	\n"
+:		"+q"(_res), "+m"(ptr->value)
+:
+:		"memory");
 	return _res == 0;
 }
 
@@ -172,8 +170,7 @@ pg_atomic_clear_flag_impl(volatile pg_atomic_flag *ptr)
 	 * On a TSO architecture like x86 it's sufficient to use a compiler
 	 * barrier to achieve release semantics.
 	 */
-	__asm__		__volatile__("":::"memory");
-
+	__asm__ __volatile__("" ::: "memory");
 	ptr->value = 0;
 }
 
@@ -182,35 +179,33 @@ static inline bool
 pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
 									uint32 *expected, uint32 newval)
 {
-	char		ret;
+	char	ret;
 
 	/*
 	 * Perform cmpxchg and use the zero flag which it implicitly sets when
 	 * equal to measure the success.
 	 */
-	__asm__		__volatile__(
-								   "	lock				\n"
-										 "	cmpxchgl	%4,%5	\n"
-								   "   setz		%2		\n"
-					 :			 "=a"(*expected), "=m"(ptr->value), "=q"(ret)
-					 :			 "a"(*expected), "r"(newval), "m"(ptr->value)
-							 :			 "memory", "cc");
-
+	__asm__ __volatile__(
+		"	lock				\n"
+		"	cmpxchgl	%4,%5	\n"
+		"   setz		%2		\n"
+:		"=a" (*expected), "=m"(ptr->value), "=q" (ret)
+:		"a" (*expected), "r" (newval), "m"(ptr->value)
+:		"memory", "cc");
 	return (bool) ret;
 }
 
 #define PG_HAVE_ATOMIC_FETCH_ADD_U32
 static inline uint32
 pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
 {
-	uint32		res;
-	__asm__		__volatile__(
-								   "	lock				\n"
-										 "	xaddl	%0,%1		\n"
-							 :			 "=q"(res), "=m"(ptr->value)
-							 :			 "0"(add_), "m"(ptr->value)
-							 :			 "memory", "cc");
-
+	uint32 res;
+	__asm__ __volatile__(
+		"	lock				\n"
+		"	xaddl	%0,%1		\n"
+:		"=q"(res), "=m"(ptr->value)
+:		"0" (add_), "m"(ptr->value)
+:		"memory", "cc");
 	return res;
 }
 
@@ -221,44 +216,40 @@ static inline bool
 pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
 									uint64 *expected, uint64 newval)
 {
-	char		ret;
+	char	ret;
 
 	/*
 	 * Perform cmpxchg and use the zero flag which it implicitly sets when
 	 * equal to measure the success.
 	 */
-	__asm__		__volatile__(
-								   "	lock				\n"
-										 "	cmpxchgq	%4,%5	\n"
-								   "   setz		%2		\n"
-					 :			 "=a"(*expected), "=m"(ptr->value), "=q"(ret)
-					 :			 "a"(*expected), "r"(newval), "m"(ptr->value)
-							 :			 "memory", "cc");
-
+	__asm__ __volatile__(
+		"	lock				\n"
+		"	cmpxchgq	%4,%5	\n"
+		"   setz		%2		\n"
+:		"=a" (*expected), "=m"(ptr->value), "=q" (ret)
+:		"a" (*expected), "r" (newval), "m"(ptr->value)
+:		"memory", "cc");
 	return (bool) ret;
 }
 
 #define PG_HAVE_ATOMIC_FETCH_ADD_U64
 static inline uint64
 pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
 {
-	uint64		res;
-	__asm__		__volatile__(
-								   "	lock				\n"
-										 "	xaddq	%0,%1		\n"
-							 :			 "=q"(res), "=m"(ptr->value)
-							 :			 "0"(add_), "m"(ptr->value)
-							 :			 "memory", "cc");
-
+	uint64 res;
+	__asm__ __volatile__(
+		"	lock				\n"
+		"	xaddq	%0,%1		\n"
+:		"=q"(res), "=m"(ptr->value)
+:		"0" (add_), "m"(ptr->value)
+:		"memory", "cc");
 	return res;
 }
 
-#endif   /* __x86_64__ */
+#endif /* __x86_64__ */
 
-#endif   /* defined(__GNUC__) &&
-								 * !defined(__INTEL_COMPILER) */
+#endif /* defined(__GNUC__) && !defined(__INTEL_COMPILER) */
 
-#endif   /* HAVE_ATOMICS */
+#endif /* HAVE_ATOMICS */
 
-#endif   /* defined(PG_USE_INLINE) ||
-								 * defined(ATOMICS_INCLUDE_DEFINITIONS) */
+#endif /* defined(PG_USE_INLINE) || defined(ATOMICS_INCLUDE_DEFINITIONS) */

src/include/port/atomics/fallback.h

@@ -1,8 +1,8 @@
 /*-------------------------------------------------------------------------
  *
  * fallback.h
- *	  Fallback for platforms without spinlock and/or atomics support. Slower
- *	  than native atomics support, but not unusably slow.
+ *    Fallback for platforms without spinlock and/or atomics support. Slower
+ *    than native atomics support, but not unusably slow.
  *
  * Portions Copyright (c) 1996-2015, PostgreSQL Global Development Group
  * Portions Copyright (c) 1994, Regents of the University of California
@@ -14,7 +14,7 @@
 
 /* intentionally no include guards, should only be included by atomics.h */
 #ifndef INSIDE_ATOMICS_H
-#error "should be included via atomics.h"
+#	error "should be included via atomics.h"
 #endif
 
 #ifndef pg_memory_barrier_impl
@@ -75,15 +75,14 @@ typedef struct pg_atomic_flag
 	 * be content with just one byte instead of 4, but that's not too much
 	 * waste.
 	 */
-#if defined(__hppa) || defined(__hppa__)		/* HP PA-RISC, GCC and HP
-												 * compilers */
+#if defined(__hppa) || defined(__hppa__)	/* HP PA-RISC, GCC and HP compilers */
 	int			sema[4];
 #else
 	int			sema;
 #endif
 } pg_atomic_flag;
 
-#endif   /* PG_HAVE_ATOMIC_FLAG_SUPPORT */
+#endif /* PG_HAVE_ATOMIC_FLAG_SUPPORT */
 
 #if !defined(PG_HAVE_ATOMIC_U32_SUPPORT)
 
@@ -93,16 +92,15 @@ typedef struct pg_atomic_flag
 typedef struct pg_atomic_uint32
 {
 	/* Check pg_atomic_flag's definition above for an explanation */
-#if defined(__hppa) || defined(__hppa__)		/* HP PA-RISC, GCC and HP
-												 * compilers */
+#if defined(__hppa) || defined(__hppa__)	/* HP PA-RISC, GCC and HP compilers */
 	int			sema[4];
 #else
 	int			sema;
 #endif
 	volatile uint32 value;
 } pg_atomic_uint32;
 
-#endif   /* PG_HAVE_ATOMIC_U32_SUPPORT */
+#endif /* PG_HAVE_ATOMIC_U32_SUPPORT */
 
 #if defined(PG_USE_INLINE) || defined(ATOMICS_INCLUDE_DEFINITIONS)
 
@@ -130,7 +128,7 @@ pg_atomic_unlocked_test_flag_impl(volatile pg_atomic_flag *ptr)
 	return true;
 }
 
-#endif   /* PG_HAVE_ATOMIC_FLAG_SIMULATION */
+#endif /* PG_HAVE_ATOMIC_FLAG_SIMULATION */
 
 #ifdef PG_HAVE_ATOMIC_U32_SIMULATION
 
@@ -139,13 +137,12 @@ extern void pg_atomic_init_u32_impl(volatile pg_atomic_uint32 *ptr, uint32 val_)
 
 #define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
 extern bool pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
-									uint32 *expected, uint32 newval);
+												uint32 *expected, uint32 newval);
 
 #define PG_HAVE_ATOMIC_FETCH_ADD_U32
 extern uint32 pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_);
 
-#endif   /* PG_HAVE_ATOMIC_U32_SIMULATION */
+#endif /* PG_HAVE_ATOMIC_U32_SIMULATION */
 
 
-#endif   /* defined(PG_USE_INLINE) ||
-								 * defined(ATOMICS_INCLUDE_DEFINITIONS) */
+#endif /* defined(PG_USE_INLINE) || defined(ATOMICS_INCLUDE_DEFINITIONS) */