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Copy pathsljitNativeS390X.c
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sljitNativeS390X.c
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/*
* Stack-less Just-In-Time compiler
*
* Copyright Zoltan Herczeg ([email protected]). All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE COPYRIGHT HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/auxv.h>
#ifdef __ARCH__
#define ENABLE_STATIC_FACILITY_DETECTION 1
#else
#define ENABLE_STATIC_FACILITY_DETECTION 0
#endif
#define ENABLE_DYNAMIC_FACILITY_DETECTION 1
SLJIT_API_FUNC_ATTRIBUTE const char* sljit_get_platform_name(void)
{
return "s390x" SLJIT_CPUINFO;
}
/* Instructions. */
typedef sljit_uw sljit_ins;
/* Instruction tags (most significant halfword). */
static const sljit_ins sljit_ins_const = (sljit_ins)1 << 48;
#define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
#define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = {
0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 0, 1
};
/* there are also a[2-15] available, but they are slower to access and
* their use is limited as mundaym explained:
* https://github.com/zherczeg/sljit/pull/91#discussion_r486895689
*/
/* General Purpose Registers [0-15]. */
typedef sljit_uw sljit_gpr;
/*
* WARNING
* the following code is non standard and should be improved for
* consistency, but doesn't use SLJIT_NUMBER_OF_REGISTERS based
* registers because r0 and r1 are the ABI recommended volatiles.
* there is a gpr() function that maps sljit to physical register numbers
* that should be used instead of the usual index into reg_map[] and
* will be retired ASAP (TODO: carenas)
*/
static const sljit_gpr r0 = 0; /* reg_map[SLJIT_NUMBER_OF_REGISTERS + 2]: 0 in address calculations; reserved */
static const sljit_gpr r1 = 1; /* reg_map[SLJIT_NUMBER_OF_REGISTERS + 3]: reserved */
static const sljit_gpr r2 = 2; /* reg_map[1]: 1st argument */
static const sljit_gpr r3 = 3; /* reg_map[2]: 2nd argument */
static const sljit_gpr r4 = 4; /* reg_map[3]: 3rd argument */
static const sljit_gpr r5 = 5; /* reg_map[4]: 4th argument */
static const sljit_gpr r6 = 6; /* reg_map[5]: 5th argument; 1st saved register */
static const sljit_gpr r7 = 7; /* reg_map[6] */
static const sljit_gpr r8 = 8; /* reg_map[7] */
static const sljit_gpr r9 = 9; /* reg_map[8] */
static const sljit_gpr r10 = 10; /* reg_map[9] */
static const sljit_gpr r11 = 11; /* reg_map[10] */
static const sljit_gpr r12 = 12; /* reg_map[11]: GOT */
static const sljit_gpr r13 = 13; /* reg_map[12]: Literal Pool pointer */
static const sljit_gpr r14 = 14; /* reg_map[0]: return address and flag register */
static const sljit_gpr r15 = 15; /* reg_map[SLJIT_NUMBER_OF_REGISTERS + 1]: stack pointer */
/* WARNING: r12 and r13 shouldn't be used as per ABI recommendation */
/* TODO(carenas): r12 might conflict in PIC code, reserve? */
/* TODO(carenas): r13 is usually pointed to "pool" per ABI, using a tmp
* like we do know might be faster though, reserve?
*/
/* TODO(carenas): should be named TMP_REG[1-2] for consistency */
#define tmp0 r0
#define tmp1 r1
/* TODO(carenas): flags should move to a different register so that
* link register doesn't need to change
*/
/* When reg cannot be unused. */
#define IS_GPR_REG(reg) ((reg > 0) && (reg) <= SLJIT_SP)
/* Link registers. The normal link register is r14, but since
we use that for flags we need to use r0 instead to do fast
calls so that flags are preserved. */
static const sljit_gpr link_r = 14; /* r14 */
static const sljit_gpr fast_link_r = 0; /* r0 */
#define TMP_FREG1 (0)
static const sljit_u8 freg_map[SLJIT_NUMBER_OF_FLOAT_REGISTERS + 1] = {
1, 0, 2, 4, 6, 3, 5, 7, 15, 14, 13, 12, 11, 10, 9, 8,
};
#define R0A(r) (r)
#define R4A(r) ((r) << 4)
#define R8A(r) ((r) << 8)
#define R12A(r) ((r) << 12)
#define R16A(r) ((r) << 16)
#define R20A(r) ((r) << 20)
#define R28A(r) ((r) << 28)
#define R32A(r) ((r) << 32)
#define R36A(r) ((r) << 36)
#define R0(r) ((sljit_ins)reg_map[r])
#define F0(r) ((sljit_ins)freg_map[r])
#define F4(r) (R4A((sljit_ins)freg_map[r]))
#define F20(r) (R20A((sljit_ins)freg_map[r]))
#define F36(r) (R36A((sljit_ins)freg_map[r]))
struct sljit_s390x_const {
struct sljit_const const_; /* must be first */
sljit_sw init_value; /* required to build literal pool */
};
/* Convert SLJIT register to hardware register. */
static SLJIT_INLINE sljit_gpr gpr(sljit_s32 r)
{
SLJIT_ASSERT(r >= 0 && r < (sljit_s32)(sizeof(reg_map) / sizeof(reg_map[0])));
return reg_map[r];
}
static SLJIT_INLINE sljit_gpr fgpr(sljit_s32 r)
{
SLJIT_ASSERT(r >= 0 && r < (sljit_s32)(sizeof(freg_map) / sizeof(freg_map[0])));
return freg_map[r];
}
/* Size of instruction in bytes. Tags must already be cleared. */
static SLJIT_INLINE sljit_uw sizeof_ins(sljit_ins ins)
{
/* keep faulting instructions */
if (ins == 0)
return 2;
if ((ins & 0x00000000ffffL) == ins)
return 2;
if ((ins & 0x0000ffffffffL) == ins)
return 4;
if ((ins & 0xffffffffffffL) == ins)
return 6;
SLJIT_UNREACHABLE();
return (sljit_uw)-1;
}
static sljit_s32 push_inst(struct sljit_compiler *compiler, sljit_ins ins)
{
sljit_ins *ibuf = (sljit_ins *)ensure_buf(compiler, sizeof(sljit_ins));
FAIL_IF(!ibuf);
*ibuf = ins;
compiler->size++;
return SLJIT_SUCCESS;
}
static sljit_s32 encode_inst(void **ptr, sljit_ins ins)
{
sljit_u16 *ibuf = (sljit_u16 *)*ptr;
sljit_uw size = sizeof_ins(ins);
SLJIT_ASSERT((size & 6) == size);
switch (size) {
case 6:
*ibuf++ = (sljit_u16)(ins >> 32);
/* fallthrough */
case 4:
*ibuf++ = (sljit_u16)(ins >> 16);
/* fallthrough */
case 2:
*ibuf++ = (sljit_u16)(ins);
}
*ptr = (void*)ibuf;
return SLJIT_SUCCESS;
}
#define SLJIT_ADD_SUB_NO_COMPARE(status_flags_state) \
(((status_flags_state) & (SLJIT_CURRENT_FLAGS_ADD | SLJIT_CURRENT_FLAGS_SUB)) \
&& !((status_flags_state) & SLJIT_CURRENT_FLAGS_COMPARE))
/* Map the given type to a 4-bit condition code mask. */
static SLJIT_INLINE sljit_u8 get_cc(struct sljit_compiler *compiler, sljit_s32 type) {
const sljit_u8 cc0 = 1 << 3; /* equal {,to zero} */
const sljit_u8 cc1 = 1 << 2; /* less than {,zero} */
const sljit_u8 cc2 = 1 << 1; /* greater than {,zero} */
const sljit_u8 cc3 = 1 << 0; /* {overflow,NaN} */
switch (type) {
case SLJIT_EQUAL:
if (SLJIT_ADD_SUB_NO_COMPARE(compiler->status_flags_state)) {
sljit_s32 type = GET_FLAG_TYPE(compiler->status_flags_state);
if (type >= SLJIT_SIG_LESS && type <= SLJIT_SIG_LESS_EQUAL)
return cc0;
if (type == SLJIT_OVERFLOW)
return (cc0 | cc3);
return (cc0 | cc2);
}
/* fallthrough */
case SLJIT_EQUAL_F64:
return cc0;
case SLJIT_NOT_EQUAL:
if (SLJIT_ADD_SUB_NO_COMPARE(compiler->status_flags_state)) {
sljit_s32 type = GET_FLAG_TYPE(compiler->status_flags_state);
if (type >= SLJIT_SIG_LESS && type <= SLJIT_SIG_LESS_EQUAL)
return (cc1 | cc2 | cc3);
if (type == SLJIT_OVERFLOW)
return (cc1 | cc2);
return (cc1 | cc3);
}
/* fallthrough */
case SLJIT_NOT_EQUAL_F64:
return (cc1 | cc2 | cc3);
case SLJIT_LESS:
return cc1;
case SLJIT_GREATER_EQUAL:
return (cc0 | cc2 | cc3);
case SLJIT_GREATER:
if (compiler->status_flags_state & SLJIT_CURRENT_FLAGS_COMPARE)
return cc2;
return cc3;
case SLJIT_LESS_EQUAL:
if (compiler->status_flags_state & SLJIT_CURRENT_FLAGS_COMPARE)
return (cc0 | cc1);
return (cc0 | cc1 | cc2);
case SLJIT_SIG_LESS:
case SLJIT_LESS_F64:
return cc1;
case SLJIT_NOT_CARRY:
if (compiler->status_flags_state & SLJIT_CURRENT_FLAGS_SUB)
return (cc2 | cc3);
/* fallthrough */
case SLJIT_SIG_LESS_EQUAL:
case SLJIT_LESS_EQUAL_F64:
return (cc0 | cc1);
case SLJIT_CARRY:
if (compiler->status_flags_state & SLJIT_CURRENT_FLAGS_SUB)
return (cc0 | cc1);
/* fallthrough */
case SLJIT_SIG_GREATER:
/* Overflow is considered greater, see SLJIT_SUB. */
return cc2 | cc3;
case SLJIT_SIG_GREATER_EQUAL:
return (cc0 | cc2 | cc3);
case SLJIT_OVERFLOW:
if (compiler->status_flags_state & SLJIT_SET_Z)
return (cc2 | cc3);
/* fallthrough */
case SLJIT_UNORDERED_F64:
return cc3;
case SLJIT_NOT_OVERFLOW:
if (compiler->status_flags_state & SLJIT_SET_Z)
return (cc0 | cc1);
/* fallthrough */
case SLJIT_ORDERED_F64:
return (cc0 | cc1 | cc2);
case SLJIT_GREATER_F64:
return cc2;
case SLJIT_GREATER_EQUAL_F64:
return (cc0 | cc2);
}
SLJIT_UNREACHABLE();
return (sljit_u8)-1;
}
/* Facility to bit index mappings.
Note: some facilities share the same bit index. */
typedef sljit_uw facility_bit;
#define STORE_FACILITY_LIST_EXTENDED_FACILITY 7
#define FAST_LONG_DISPLACEMENT_FACILITY 19
#define EXTENDED_IMMEDIATE_FACILITY 21
#define GENERAL_INSTRUCTION_EXTENSION_FACILITY 34
#define DISTINCT_OPERAND_FACILITY 45
#define HIGH_WORD_FACILITY 45
#define POPULATION_COUNT_FACILITY 45
#define LOAD_STORE_ON_CONDITION_1_FACILITY 45
#define MISCELLANEOUS_INSTRUCTION_EXTENSIONS_1_FACILITY 49
#define LOAD_STORE_ON_CONDITION_2_FACILITY 53
#define MISCELLANEOUS_INSTRUCTION_EXTENSIONS_2_FACILITY 58
#define VECTOR_FACILITY 129
#define VECTOR_ENHANCEMENTS_1_FACILITY 135
/* Report whether a facility is known to be present due to the compiler
settings. This function should always be compiled to a constant
value given a constant argument. */
static SLJIT_INLINE int have_facility_static(facility_bit x)
{
#if ENABLE_STATIC_FACILITY_DETECTION
switch (x) {
case FAST_LONG_DISPLACEMENT_FACILITY:
return (__ARCH__ >= 6 /* z990 */);
case EXTENDED_IMMEDIATE_FACILITY:
case STORE_FACILITY_LIST_EXTENDED_FACILITY:
return (__ARCH__ >= 7 /* z9-109 */);
case GENERAL_INSTRUCTION_EXTENSION_FACILITY:
return (__ARCH__ >= 8 /* z10 */);
case DISTINCT_OPERAND_FACILITY:
return (__ARCH__ >= 9 /* z196 */);
case MISCELLANEOUS_INSTRUCTION_EXTENSIONS_1_FACILITY:
return (__ARCH__ >= 10 /* zEC12 */);
case LOAD_STORE_ON_CONDITION_2_FACILITY:
case VECTOR_FACILITY:
return (__ARCH__ >= 11 /* z13 */);
case MISCELLANEOUS_INSTRUCTION_EXTENSIONS_2_FACILITY:
case VECTOR_ENHANCEMENTS_1_FACILITY:
return (__ARCH__ >= 12 /* z14 */);
default:
SLJIT_UNREACHABLE();
}
#endif
return 0;
}
static SLJIT_INLINE unsigned long get_hwcap()
{
static unsigned long hwcap = 0;
if (SLJIT_UNLIKELY(!hwcap)) {
hwcap = getauxval(AT_HWCAP);
SLJIT_ASSERT(hwcap != 0);
}
return hwcap;
}
static SLJIT_INLINE int have_stfle()
{
if (have_facility_static(STORE_FACILITY_LIST_EXTENDED_FACILITY))
return 1;
return (get_hwcap() & HWCAP_S390_STFLE);
}
/* Report whether the given facility is available. This function always
performs a runtime check. */
static int have_facility_dynamic(facility_bit x)
{
#if ENABLE_DYNAMIC_FACILITY_DETECTION
static struct {
sljit_uw bits[4];
} cpu_features;
size_t size = sizeof(cpu_features);
const sljit_uw word_index = x >> 6;
const sljit_uw bit_index = ((1UL << 63) >> (x & 63));
SLJIT_ASSERT(x < size * 8);
if (SLJIT_UNLIKELY(!have_stfle()))
return 0;
if (SLJIT_UNLIKELY(cpu_features.bits[0] == 0)) {
__asm__ __volatile__ (
"lgr %%r0, %0;"
"stfle 0(%1);"
/* outputs */:
/* inputs */: "d" ((size / 8) - 1), "a" (&cpu_features)
/* clobbers */: "r0", "cc", "memory"
);
SLJIT_ASSERT(cpu_features.bits[0] != 0);
}
return (cpu_features.bits[word_index] & bit_index) != 0;
#else
return 0;
#endif
}
#define HAVE_FACILITY(name, bit) \
static SLJIT_INLINE int name() \
{ \
static int have = -1; \
/* Static check first. May allow the function to be optimized away. */ \
if (have_facility_static(bit)) \
have = 1; \
else if (SLJIT_UNLIKELY(have < 0)) \
have = have_facility_dynamic(bit) ? 1 : 0; \
\
return have; \
}
HAVE_FACILITY(have_eimm, EXTENDED_IMMEDIATE_FACILITY)
HAVE_FACILITY(have_ldisp, FAST_LONG_DISPLACEMENT_FACILITY)
HAVE_FACILITY(have_genext, GENERAL_INSTRUCTION_EXTENSION_FACILITY)
HAVE_FACILITY(have_lscond1, LOAD_STORE_ON_CONDITION_1_FACILITY)
HAVE_FACILITY(have_lscond2, LOAD_STORE_ON_CONDITION_2_FACILITY)
HAVE_FACILITY(have_misc2, MISCELLANEOUS_INSTRUCTION_EXTENSIONS_2_FACILITY)
#undef HAVE_FACILITY
#define is_u12(d) (0 <= (d) && (d) <= 0x00000fffL)
#define is_u32(d) (0 <= (d) && (d) <= 0xffffffffL)
#define CHECK_SIGNED(v, bitlen) \
((v) >= -(1 << ((bitlen) - 1)) && (v) < (1 << ((bitlen) - 1)))
#define is_s8(d) CHECK_SIGNED((d), 8)
#define is_s16(d) CHECK_SIGNED((d), 16)
#define is_s20(d) CHECK_SIGNED((d), 20)
#define is_s32(d) ((d) == (sljit_s32)(d))
static SLJIT_INLINE sljit_ins disp_s20(sljit_s32 d)
{
SLJIT_ASSERT(is_s20(d));
sljit_uw dh = (d >> 12) & 0xff;
sljit_uw dl = (d << 8) & 0xfff00;
return (dh | dl) << 8;
}
/* TODO(carenas): variadic macro is not strictly needed */
#define SLJIT_S390X_INSTRUCTION(op, ...) \
static SLJIT_INLINE sljit_ins op(__VA_ARGS__)
/* RR form instructions. */
#define SLJIT_S390X_RR(name, pattern) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr dst, sljit_gpr src) \
{ \
return (pattern) | ((dst & 0xf) << 4) | (src & 0xf); \
}
/* AND */
SLJIT_S390X_RR(nr, 0x1400)
/* BRANCH AND SAVE */
SLJIT_S390X_RR(basr, 0x0d00)
/* BRANCH ON CONDITION */
SLJIT_S390X_RR(bcr, 0x0700) /* TODO(mundaym): type for mask? */
/* DIVIDE */
SLJIT_S390X_RR(dr, 0x1d00)
/* EXCLUSIVE OR */
SLJIT_S390X_RR(xr, 0x1700)
/* LOAD */
SLJIT_S390X_RR(lr, 0x1800)
/* LOAD COMPLEMENT */
SLJIT_S390X_RR(lcr, 0x1300)
/* OR */
SLJIT_S390X_RR(or, 0x1600)
#undef SLJIT_S390X_RR
/* RRE form instructions */
#define SLJIT_S390X_RRE(name, pattern) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr dst, sljit_gpr src) \
{ \
return (pattern) | R4A(dst) | R0A(src); \
}
/* AND */
SLJIT_S390X_RRE(ngr, 0xb9800000)
/* DIVIDE LOGICAL */
SLJIT_S390X_RRE(dlr, 0xb9970000)
SLJIT_S390X_RRE(dlgr, 0xb9870000)
/* DIVIDE SINGLE */
SLJIT_S390X_RRE(dsgr, 0xb90d0000)
/* EXCLUSIVE OR */
SLJIT_S390X_RRE(xgr, 0xb9820000)
/* LOAD */
SLJIT_S390X_RRE(lgr, 0xb9040000)
SLJIT_S390X_RRE(lgfr, 0xb9140000)
/* LOAD BYTE */
SLJIT_S390X_RRE(lbr, 0xb9260000)
SLJIT_S390X_RRE(lgbr, 0xb9060000)
/* LOAD COMPLEMENT */
SLJIT_S390X_RRE(lcgr, 0xb9030000)
/* LOAD HALFWORD */
SLJIT_S390X_RRE(lhr, 0xb9270000)
SLJIT_S390X_RRE(lghr, 0xb9070000)
/* LOAD LOGICAL */
SLJIT_S390X_RRE(llgfr, 0xb9160000)
/* LOAD LOGICAL CHARACTER */
SLJIT_S390X_RRE(llcr, 0xb9940000)
SLJIT_S390X_RRE(llgcr, 0xb9840000)
/* LOAD LOGICAL HALFWORD */
SLJIT_S390X_RRE(llhr, 0xb9950000)
SLJIT_S390X_RRE(llghr, 0xb9850000)
/* MULTIPLY LOGICAL */
SLJIT_S390X_RRE(mlgr, 0xb9860000)
/* MULTIPLY SINGLE */
SLJIT_S390X_RRE(msgfr, 0xb91c0000)
/* OR */
SLJIT_S390X_RRE(ogr, 0xb9810000)
/* SUBTRACT */
SLJIT_S390X_RRE(sgr, 0xb9090000)
#undef SLJIT_S390X_RRE
/* RI-a form instructions */
#define SLJIT_S390X_RIA(name, pattern, imm_type) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr reg, imm_type imm) \
{ \
return (pattern) | R20A(reg) | (imm & 0xffff); \
}
/* ADD HALFWORD IMMEDIATE */
SLJIT_S390X_RIA(aghi, 0xa70b0000, sljit_s16)
/* LOAD HALFWORD IMMEDIATE */
SLJIT_S390X_RIA(lhi, 0xa7080000, sljit_s16)
SLJIT_S390X_RIA(lghi, 0xa7090000, sljit_s16)
/* LOAD LOGICAL IMMEDIATE */
SLJIT_S390X_RIA(llihh, 0xa50c0000, sljit_u16)
SLJIT_S390X_RIA(llihl, 0xa50d0000, sljit_u16)
SLJIT_S390X_RIA(llilh, 0xa50e0000, sljit_u16)
SLJIT_S390X_RIA(llill, 0xa50f0000, sljit_u16)
/* MULTIPLY HALFWORD IMMEDIATE */
SLJIT_S390X_RIA(mhi, 0xa70c0000, sljit_s16)
SLJIT_S390X_RIA(mghi, 0xa70d0000, sljit_s16)
/* OR IMMEDIATE */
SLJIT_S390X_RIA(oilh, 0xa50a0000, sljit_u16)
#undef SLJIT_S390X_RIA
/* RIL-a form instructions (requires extended immediate facility) */
#define SLJIT_S390X_RILA(name, pattern, imm_type) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr reg, imm_type imm) \
{ \
SLJIT_ASSERT(have_eimm()); \
return (pattern) | R36A(reg) | ((sljit_ins)imm & 0xffffffffu); \
}
/* ADD IMMEDIATE */
SLJIT_S390X_RILA(agfi, 0xc20800000000, sljit_s32)
/* ADD IMMEDIATE HIGH */
SLJIT_S390X_RILA(aih, 0xcc0800000000, sljit_s32) /* TODO(mundaym): high-word facility? */
/* AND IMMEDIATE */
SLJIT_S390X_RILA(nihf, 0xc00a00000000, sljit_u32)
/* EXCLUSIVE OR IMMEDIATE */
SLJIT_S390X_RILA(xilf, 0xc00700000000, sljit_u32)
/* INSERT IMMEDIATE */
SLJIT_S390X_RILA(iihf, 0xc00800000000, sljit_u32)
SLJIT_S390X_RILA(iilf, 0xc00900000000, sljit_u32)
/* LOAD IMMEDIATE */
SLJIT_S390X_RILA(lgfi, 0xc00100000000, sljit_s32)
/* LOAD LOGICAL IMMEDIATE */
SLJIT_S390X_RILA(llihf, 0xc00e00000000, sljit_u32)
SLJIT_S390X_RILA(llilf, 0xc00f00000000, sljit_u32)
/* SUBTRACT LOGICAL IMMEDIATE */
SLJIT_S390X_RILA(slfi, 0xc20500000000, sljit_u32)
#undef SLJIT_S390X_RILA
/* RX-a form instructions */
#define SLJIT_S390X_RXA(name, pattern) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr r, sljit_s32 d, sljit_gpr x, sljit_gpr b) \
{ \
SLJIT_ASSERT((d & 0xfff) == d); \
\
return (pattern) | R20A(r) | R16A(x) | R12A(b) | (sljit_ins)(d & 0xfff); \
}
/* LOAD */
SLJIT_S390X_RXA(l, 0x58000000)
/* LOAD ADDRESS */
SLJIT_S390X_RXA(la, 0x41000000)
/* LOAD HALFWORD */
SLJIT_S390X_RXA(lh, 0x48000000)
/* MULTIPLY SINGLE */
SLJIT_S390X_RXA(ms, 0x71000000)
/* STORE */
SLJIT_S390X_RXA(st, 0x50000000)
/* STORE CHARACTER */
SLJIT_S390X_RXA(stc, 0x42000000)
/* STORE HALFWORD */
SLJIT_S390X_RXA(sth, 0x40000000)
#undef SLJIT_S390X_RXA
/* RXY-a instructions */
#define SLJIT_S390X_RXYA(name, pattern, cond) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr r, sljit_s32 d, sljit_gpr x, sljit_gpr b) \
{ \
SLJIT_ASSERT(cond); \
\
return (pattern) | R36A(r) | R32A(x) | R28A(b) | disp_s20(d); \
}
/* LOAD */
SLJIT_S390X_RXYA(ly, 0xe30000000058, have_ldisp())
SLJIT_S390X_RXYA(lg, 0xe30000000004, 1)
SLJIT_S390X_RXYA(lgf, 0xe30000000014, 1)
/* LOAD BYTE */
SLJIT_S390X_RXYA(lb, 0xe30000000076, have_ldisp())
SLJIT_S390X_RXYA(lgb, 0xe30000000077, have_ldisp())
/* LOAD HALFWORD */
SLJIT_S390X_RXYA(lhy, 0xe30000000078, have_ldisp())
SLJIT_S390X_RXYA(lgh, 0xe30000000015, 1)
/* LOAD LOGICAL */
SLJIT_S390X_RXYA(llgf, 0xe30000000016, 1)
/* LOAD LOGICAL CHARACTER */
SLJIT_S390X_RXYA(llc, 0xe30000000094, have_eimm())
SLJIT_S390X_RXYA(llgc, 0xe30000000090, 1)
/* LOAD LOGICAL HALFWORD */
SLJIT_S390X_RXYA(llh, 0xe30000000095, have_eimm())
SLJIT_S390X_RXYA(llgh, 0xe30000000091, 1)
/* MULTIPLY SINGLE */
SLJIT_S390X_RXYA(msy, 0xe30000000051, have_ldisp())
SLJIT_S390X_RXYA(msg, 0xe3000000000c, 1)
/* STORE */
SLJIT_S390X_RXYA(sty, 0xe30000000050, have_ldisp())
SLJIT_S390X_RXYA(stg, 0xe30000000024, 1)
/* STORE CHARACTER */
SLJIT_S390X_RXYA(stcy, 0xe30000000072, have_ldisp())
/* STORE HALFWORD */
SLJIT_S390X_RXYA(sthy, 0xe30000000070, have_ldisp())
#undef SLJIT_S390X_RXYA
/* RSY-a instructions */
#define SLJIT_S390X_RSYA(name, pattern, cond) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr dst, sljit_gpr src, sljit_s32 d, sljit_gpr b) \
{ \
SLJIT_ASSERT(cond); \
\
return (pattern) | R36A(dst) | R32A(src) | R28A(b) | disp_s20(d); \
}
/* LOAD MULTIPLE */
SLJIT_S390X_RSYA(lmg, 0xeb0000000004, 1)
/* SHIFT LEFT LOGICAL */
SLJIT_S390X_RSYA(sllg, 0xeb000000000d, 1)
/* SHIFT RIGHT SINGLE */
SLJIT_S390X_RSYA(srag, 0xeb000000000a, 1)
/* STORE MULTIPLE */
SLJIT_S390X_RSYA(stmg, 0xeb0000000024, 1)
#undef SLJIT_S390X_RSYA
/* RIE-f instructions (require general-instructions-extension facility) */
#define SLJIT_S390X_RIEF(name, pattern) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr dst, sljit_gpr src, sljit_u8 start, sljit_u8 end, sljit_u8 rot) \
{ \
sljit_ins i3, i4, i5; \
\
SLJIT_ASSERT(have_genext()); \
i3 = (sljit_ins)start << 24; \
i4 = (sljit_ins)end << 16; \
i5 = (sljit_ins)rot << 8; \
\
return (pattern) | R36A(dst & 0xf) | R32A(src & 0xf) | i3 | i4 | i5; \
}
/* ROTATE THEN AND SELECTED BITS */
/* SLJIT_S390X_RIEF(rnsbg, 0xec0000000054) */
/* ROTATE THEN EXCLUSIVE OR SELECTED BITS */
/* SLJIT_S390X_RIEF(rxsbg, 0xec0000000057) */
/* ROTATE THEN OR SELECTED BITS */
SLJIT_S390X_RIEF(rosbg, 0xec0000000056)
/* ROTATE THEN INSERT SELECTED BITS */
/* SLJIT_S390X_RIEF(risbg, 0xec0000000055) */
/* SLJIT_S390X_RIEF(risbgn, 0xec0000000059) */
/* ROTATE THEN INSERT SELECTED BITS HIGH */
SLJIT_S390X_RIEF(risbhg, 0xec000000005d)
/* ROTATE THEN INSERT SELECTED BITS LOW */
/* SLJIT_S390X_RIEF(risblg, 0xec0000000051) */
#undef SLJIT_S390X_RIEF
/* RRF-c instructions (require load/store-on-condition 1 facility) */
#define SLJIT_S390X_RRFC(name, pattern) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr dst, sljit_gpr src, sljit_uw mask) \
{ \
sljit_ins m3; \
\
SLJIT_ASSERT(have_lscond1()); \
m3 = (sljit_ins)(mask & 0xf) << 12; \
\
return (pattern) | m3 | R4A(dst) | R0A(src); \
}
/* LOAD HALFWORD IMMEDIATE ON CONDITION */
SLJIT_S390X_RRFC(locr, 0xb9f20000)
SLJIT_S390X_RRFC(locgr, 0xb9e20000)
#undef SLJIT_S390X_RRFC
/* RIE-g instructions (require load/store-on-condition 2 facility) */
#define SLJIT_S390X_RIEG(name, pattern) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr reg, sljit_sw imm, sljit_uw mask) \
{ \
sljit_ins m3, i2; \
\
SLJIT_ASSERT(have_lscond2()); \
m3 = (sljit_ins)(mask & 0xf) << 32; \
i2 = (sljit_ins)(imm & 0xffffL) << 16; \
\
return (pattern) | R36A(reg) | m3 | i2; \
}
/* LOAD HALFWORD IMMEDIATE ON CONDITION */
SLJIT_S390X_RIEG(lochi, 0xec0000000042)
SLJIT_S390X_RIEG(locghi, 0xec0000000046)
#undef SLJIT_S390X_RIEG
#define SLJIT_S390X_RILB(name, pattern, cond) \
SLJIT_S390X_INSTRUCTION(name, sljit_gpr reg, sljit_sw ri) \
{ \
SLJIT_ASSERT(cond); \
\
return (pattern) | R36A(reg) | (sljit_ins)(ri & 0xffffffff); \
}
/* BRANCH RELATIVE AND SAVE LONG */
SLJIT_S390X_RILB(brasl, 0xc00500000000, 1)
/* LOAD ADDRESS RELATIVE LONG */
SLJIT_S390X_RILB(larl, 0xc00000000000, 1)
/* LOAD RELATIVE LONG */
SLJIT_S390X_RILB(lgrl, 0xc40800000000, have_genext())
#undef SLJIT_S390X_RILB
SLJIT_S390X_INSTRUCTION(br, sljit_gpr target)
{
return 0x07f0 | target;
}
SLJIT_S390X_INSTRUCTION(brc, sljit_uw mask, sljit_sw target)
{
sljit_ins m1 = (sljit_ins)(mask & 0xf) << 20;
sljit_ins ri2 = (sljit_ins)target & 0xffff;
return 0xa7040000L | m1 | ri2;
}
SLJIT_S390X_INSTRUCTION(brcl, sljit_uw mask, sljit_sw target)
{
sljit_ins m1 = (sljit_ins)(mask & 0xf) << 36;
sljit_ins ri2 = (sljit_ins)target & 0xffffffff;
return 0xc00400000000L | m1 | ri2;
}
SLJIT_S390X_INSTRUCTION(flogr, sljit_gpr dst, sljit_gpr src)
{
SLJIT_ASSERT(have_eimm());
return 0xb9830000 | R8A(dst) | R0A(src);
}
/* INSERT PROGRAM MASK */
SLJIT_S390X_INSTRUCTION(ipm, sljit_gpr dst)
{
return 0xb2220000 | R4A(dst);
}
/* SET PROGRAM MASK */
SLJIT_S390X_INSTRUCTION(spm, sljit_gpr dst)
{
return 0x0400 | R4A(dst);
}
/* ROTATE THEN INSERT SELECTED BITS HIGH (ZERO) */
SLJIT_S390X_INSTRUCTION(risbhgz, sljit_gpr dst, sljit_gpr src, sljit_u8 start, sljit_u8 end, sljit_u8 rot)
{
return risbhg(dst, src, start, 0x8 | end, rot);
}
#undef SLJIT_S390X_INSTRUCTION
static sljit_s32 update_zero_overflow(struct sljit_compiler *compiler, sljit_s32 op, sljit_gpr dst_r)
{
/* Condition codes: bits 18 and 19.
Transformation:
0 (zero and no overflow) : unchanged
1 (non-zero and no overflow) : unchanged
2 (zero and overflow) : decreased by 1
3 (non-zero and overflow) : decreased by 1 if non-zero */
FAIL_IF(push_inst(compiler, brc(0xc, 2 + 2 + ((op & SLJIT_32) ? 1 : 2) + 2 + 3 + 1)));
FAIL_IF(push_inst(compiler, ipm(tmp1)));
FAIL_IF(push_inst(compiler, (op & SLJIT_32) ? or(dst_r, dst_r) : ogr(dst_r, dst_r)));
FAIL_IF(push_inst(compiler, brc(0x8, 2 + 3)));
FAIL_IF(push_inst(compiler, slfi(tmp1, 0x10000000)));
FAIL_IF(push_inst(compiler, spm(tmp1)));
return SLJIT_SUCCESS;
}
/* load 64-bit immediate into register without clobbering flags */
static sljit_s32 push_load_imm_inst(struct sljit_compiler *compiler, sljit_gpr target, sljit_sw v)
{
/* 4 byte instructions */
if (is_s16(v))
return push_inst(compiler, lghi(target, (sljit_s16)v));
if (((sljit_uw)v & ~(sljit_uw)0x000000000000ffff) == 0)
return push_inst(compiler, llill(target, (sljit_u16)v));
if (((sljit_uw)v & ~(sljit_uw)0x00000000ffff0000) == 0)
return push_inst(compiler, llilh(target, (sljit_u16)(v >> 16)));
if (((sljit_uw)v & ~(sljit_uw)0x0000ffff00000000) == 0)
return push_inst(compiler, llihl(target, (sljit_u16)(v >> 32)));
if (((sljit_uw)v & ~(sljit_uw)0xffff000000000000) == 0)
return push_inst(compiler, llihh(target, (sljit_u16)(v >> 48)));
/* 6 byte instructions (requires extended immediate facility) */
if (have_eimm()) {
if (is_s32(v))
return push_inst(compiler, lgfi(target, (sljit_s32)v));
if (((sljit_uw)v >> 32) == 0)
return push_inst(compiler, llilf(target, (sljit_u32)v));
if (((sljit_uw)v << 32) == 0)
return push_inst(compiler, llihf(target, (sljit_u32)((sljit_uw)v >> 32)));
FAIL_IF(push_inst(compiler, llilf(target, (sljit_u32)v)));
return push_inst(compiler, iihf(target, (sljit_u32)(v >> 32)));
}
/* TODO(mundaym): instruction sequences that don't use extended immediates */
abort();
}
struct addr {
sljit_gpr base;
sljit_gpr index;
sljit_s32 offset;
};
/* transform memory operand into D(X,B) form with a signed 20-bit offset */
static sljit_s32 make_addr_bxy(struct sljit_compiler *compiler,
struct addr *addr, sljit_s32 mem, sljit_sw off,
sljit_gpr tmp /* clobbered, must not be r0 */)
{
sljit_gpr base = r0;
sljit_gpr index = r0;
SLJIT_ASSERT(tmp != r0);
if (mem & REG_MASK)
base = gpr(mem & REG_MASK);
if (mem & OFFS_REG_MASK) {
index = gpr(OFFS_REG(mem));
if (off != 0) {
/* shift and put the result into tmp */
SLJIT_ASSERT(0 <= off && off < 64);
FAIL_IF(push_inst(compiler, sllg(tmp, index, (sljit_s32)off, 0)));
index = tmp;
off = 0; /* clear offset */
}
}
else if (!is_s20(off)) {
FAIL_IF(push_load_imm_inst(compiler, tmp, off));
index = tmp;
off = 0; /* clear offset */
}
addr->base = base;
addr->index = index;
addr->offset = (sljit_s32)off;
return SLJIT_SUCCESS;
}
/* transform memory operand into D(X,B) form with an unsigned 12-bit offset */
static sljit_s32 make_addr_bx(struct sljit_compiler *compiler,
struct addr *addr, sljit_s32 mem, sljit_sw off,
sljit_gpr tmp /* clobbered, must not be r0 */)
{
sljit_gpr base = r0;
sljit_gpr index = r0;
SLJIT_ASSERT(tmp != r0);
if (mem & REG_MASK)
base = gpr(mem & REG_MASK);
if (mem & OFFS_REG_MASK) {
index = gpr(OFFS_REG(mem));
if (off != 0) {
/* shift and put the result into tmp */
SLJIT_ASSERT(0 <= off && off < 64);
FAIL_IF(push_inst(compiler, sllg(tmp, index, (sljit_s32)off, 0)));
index = tmp;
off = 0; /* clear offset */
}
}
else if (!is_u12(off)) {
FAIL_IF(push_load_imm_inst(compiler, tmp, off));
index = tmp;
off = 0; /* clear offset */
}
addr->base = base;
addr->index = index;
addr->offset = (sljit_s32)off;
return SLJIT_SUCCESS;
}
#define EVAL(op, r, addr) op(r, addr.offset, addr.index, addr.base)
#define WHEN(cond, r, i1, i2, addr) \
(cond) ? EVAL(i1, r, addr) : EVAL(i2, r, addr)
/* May clobber tmp1. */
static sljit_s32 load_word(struct sljit_compiler *compiler, sljit_gpr dst,
sljit_s32 src, sljit_sw srcw,
sljit_s32 is_32bit)
{
struct addr addr;
sljit_ins ins;
SLJIT_ASSERT(src & SLJIT_MEM);
if (have_ldisp() || !is_32bit)
FAIL_IF(make_addr_bxy(compiler, &addr, src, srcw, tmp1));
else
FAIL_IF(make_addr_bx(compiler, &addr, src, srcw, tmp1));
if (is_32bit)
ins = WHEN(is_u12(addr.offset), dst, l, ly, addr);
else
ins = lg(dst, addr.offset, addr.index, addr.base);
return push_inst(compiler, ins);
}