This repository was archived by the owner on Apr 23, 2020. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 2.1k
/
Copy pathand_or.ll
149 lines (142 loc) · 4.76 KB
/
and_or.ll
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
; ===================================================================================
; V_AND_OR_B32
; ===================================================================================
define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
; VI-LABEL: and_or:
; VI: ; %bb.0:
; VI-NEXT: v_and_b32_e32 v0, v0, v1
; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: and_or:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
ret float %bc
}
; ThreeOp instruction variant not used due to Constant Bus Limitations
define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
; VI-LABEL: and_or_vgpr_b:
; VI: ; %bb.0:
; VI-NEXT: v_and_b32_e32 v0, s2, v0
; VI-NEXT: v_or_b32_e32 v0, s3, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_b:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_b:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s3
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
ret float %bc
}
define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
; VI-LABEL: and_or_vgpr_ab:
; VI: ; %bb.0:
; VI-NEXT: v_and_b32_e32 v0, v0, v1
; VI-NEXT: v_or_b32_e32 v0, s2, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_ab:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_ab:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
ret float %bc
}
define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
; VI-LABEL: and_or_vgpr_const:
; VI: ; %bb.0:
; VI-NEXT: v_and_b32_e32 v0, 4, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_const:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 4, %a
%result = or i32 %x, %b
%bc = bitcast i32 %result to float
ret float %bc
}
define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
; VI-LABEL: and_or_vgpr_const_inline_const:
; VI: ; %bb.0:
; VI-NEXT: v_and_b32_e32 v0, 20, v0
; VI-NEXT: v_or_b32_e32 v0, 0x808, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_const_inline_const:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, 0x808
; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_const_inline_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 20, %a
%result = or i32 %x, 2056
%bc = bitcast i32 %result to float
ret float %bc
}
define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
; VI-LABEL: and_or_vgpr_inline_const_x2:
; VI: ; %bb.0:
; VI-NEXT: v_and_b32_e32 v0, 4, v0
; VI-NEXT: v_or_b32_e32 v0, 1, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_inline_const_x2:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_inline_const_x2:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 4, %a
%result = or i32 %x, 1
%bc = bitcast i32 %result to float
ret float %bc
}