hardware-sprites

Hardware Sprites

This folder accompanies the Project F blog post: Hardware Sprites. These SystemVerilog designs create fast, colourful, graphics with minimal logic. You can freely build on these MIT licensed designs. Have fun.

File layout:

• ice40 - designs for iCEBreaker and other Lattice iCE40 boards
• res - resources: sprite bitmaps and palettes
• sim - simulation with Verilator and LibSDL; see the Simulation README
• xc7 - designs for Arty and other Xilinx 7 Series boards with VGA output
• xc7-dvi - designs for Nexys Video and other Xilinx 7 Series boards with DVI output

These designs make use of modules from the Project F library. Check the included iCE40 Makefile or Vivado create_project.tcl to see the list of modules used.

Demos

• Tiny F - monochrome 8x8 pixel 'F' sprite
  • Inline - inline Verilog graphic
  • ROM - async ROM graphic
  • Scale - sprite scaling
  • Move - sprite moving
• Hourglass - 16-colour 8x8 pixel hourglass sprite
• Hedgehog - 16 colour hedgehog sprite

Learn more about the designs and demos from Hardware Sprites, or read on for build instructions.

Hedgehog sprite video capture from Nexys Video.

iCEBreaker Build

You can build projects for iCEBreaker using the included Makefile with Yosys, nextpnr, and IceStorm Tools.

You can get pre-built tool binaries for Linux, Mac, and Windows from YosysHQ. If you want to build the tools yourself, check out Building iCE40 FPGA Toolchain on Linux.

For example, to build hedgehog; clone the projf-explore git repo, then:

cd projf-explore/graphics/hardware-sprites/ice40
make hedgehog

After the build completes, you'll have a bin file, such as hedgehog.bin. Use the bin file to program your board:

iceprog hedgehog.bin

If you get the error Can't find iCE FTDI USB device, try running iceprog with sudo.

Problems Building

If you have problems building the iCE40 designs, make sure you're using Yosys 0.10 or later.

Arty Build

To create a Vivado project for the Digilent Arty (original or A7-35T); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/graphics/hardware-sprites/xc7/vivado
source ./create_project.tcl

You can then build the demos as you would for any Vivado project.

Behavioural Simulation

This design includes test benches for the updated display module, CLUT, and sprites modules. You can run the test bench simulations from the GUI under the "Flow" menu or from the Tcl Console with:

launch_simulation
run all

By default, the display_480p test bench is run, but you can switch to other test benches using the GUI or from the Tcl console:

set fs_sim_obj [get_filesets sim_1]
set_property -name "top" -value "sprite_tb" -objects $fs_sim_obj
relaunch_sim
run all

This example switches to sprite_tb; replace this name with the test bench you want.

Other Xilinx 7 Series Boards

It's straightforward to adapt the project for other Xilinx 7 Series boards:

1. Create a suitable constraints file named <board>.xdc within the xc7 directory
2. Make a note of your board's FPGA part, such as xc7a35ticsg324-1L
3. Set the board and part names in Tcl, then source the create project script:

set board_name <board>
set fpga_part <fpga-part>
cd projf-explore/graphics/hardware-sprites/xc7/vivado
source ./create_project.tcl

Replace <board> and <fpga-part> with the actual board and part names.

Nexys Video Build

To create a Vivado project for the Digilent Nexys Video; clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/graphics/hardware-sprites/xc7-dvi/vivado
source ./create_project.tcl

You can then build the designs as you would for any Vivado project.

Tested Versions

The Nexys Video designs have been tested with:

• Vivado 2022.2

Verilator SDL Simulation

You can simulate these designs on your computer using Verilator and SDL. The Simulation README has build instructions.

Linting

If you have Verilator installed, you can run the linting shell script lint.sh to check the designs. Learn more from Verilog Lint with Verilator.

SystemVerilog?

These designs use a little SystemVerilog to make Verilog more pleasant. See the Library README for details of SV features used.