Paper 2024/1019
Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Towards Power and EM SCA Resilience
Abstract
Mathematically secured cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to hinder side channel leakage at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at $V_{DD}$ port. Although any digital implementation has two generic ports, namely clock and $V_{DD}$, circuit-level countermeasures primarily focus on $V_{DD}$ port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew. Due to this, minimum traces-to-disclosure (MTD) improves by 100$\times$ with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult} to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect(1800x) more than the multiplication of individual techniques (100x & 5x respectively). In brief, this paper presents a clock-level generic synthesizable countermeasure technique that improved the minimum-traces-to-disclosure (MTD) by 1800$\times$ and incurs only 11% area overhead, $<3\%$ power overhead (measured) and $<6\%$ performance overhead (measured). Moreover, this can be easily combined with other power-port-based mitigation techniques for enhanced security.
Note: This is under revision. It will be updated with publication details and an updated draft.
Metadata
- Available format(s)
- Category
- Applications
- Publication info
- Preprint.
- Keywords
- side-channel attackscorrelational power analysisTVLAgeneric countermeasureclock-based countermeasureclock-slew
- Contact author(s)
-
ghosh69 @ purdue edu
rahman88 @ purdue edu
shreyas @ purdue edu - History
- 2024-06-28: approved
- 2024-06-24: received
- See all versions
- Short URL
- https://ia.cr/2024/1019
- License
-
CC BY-NC-ND
BibTeX
@misc{cryptoeprint:2024/1019, author = {Archisman Ghosh and Md. Abdur Rahman and Debayan Das and Santosh Ghosh and Shreyas Sen}, title = {Exploiting Clock-Slew Dependent Variability in {CMOS} Digital Circuits Towards Power and {EM} {SCA} Resilience}, howpublished = {Cryptology {ePrint} Archive, Paper 2024/1019}, year = {2024}, url = {https://eprint.iacr.org/2024/1019} }