Jump to content

Gekko (processor): Difference between revisions

From Wikipedia, the free encyclopedia
Content deleted Content added
m Features: spacing fixes
References: Use {{cite press release}} for a press release.
 
(45 intermediate revisions by 29 users not shown)
Line 1: Line 1:
{{short description|CPU for the GameCube}}
{{more footnotes|date=July 2018}}
{{Infobox CPU
{{Infobox CPU
| name = Gekko
| name = Gekko
| image = GEKKO.jpg
| image = GEKKO.jpg
| image_size = frameless|upright=1.25
| image_size = frameless{{!}}upright=1.25
| caption = IBM '''Gekko''' processor
| caption = IBM '''Gekko''' processor
| produced-start = 2000
| produced-start = 2000
Line 14: Line 16:
| soldby =
| soldby =
| designfirm = [[IBM]] and [[Nintendo]]
| designfirm = [[IBM]] and [[Nintendo]]
| manuf1 = [[IBM]]
| manuf1 = [[IBM Microelectronics]]
| arch = [[Power Architecture]]
| arch = [[PowerPC|PowerPC ISA 1.10]]
| microarch = [[PowerPC G3|PowerPC ISA 1.10]]
| microarch = [[PowerPC G3]]
| code =
| code =
| numcores = 1
| numcores = 1
| l1cache = 32/32 kB
| l1cache = 32/32 KB
| l2cache = 256 kB
| l2cache = 256 KB
| l3cache =
| l3cache =
| application = [[Nintendo GameCube]]<br />[[Triforce (arcade system board)|Triforce Arcade Board]]
| application = [[GameCube]]<br />[[Triforce (arcade system board)|Triforce Arcade Board]]
| predecessor = [[R4200#R4300i|NEC VR4300]]
| predecessor = [[R4200#R4300i|NEC VR4300]]
| successor = [[Broadway (microprocessor)|Broadway]]
| successor = [[Broadway (microprocessor)|Broadway]]
| variant = * [[PowerPC G3|PowerPC 750CXe]]
| variant = * [[PowerPC G3|PowerPC 750CXe]]
}}
}}
{{Power Architecture}}


[[File:IBM Gekko Die Exposed.jpg|thumb|180nm IBM Gekko CPU in the Gamecube shaved down to expose the [[Die (integrated circuit)|silicon die]]]]
'''Gekko''' is a superscalar out-of-order [[32-bit]] [[PowerPC]] [[microprocessor]] custom-made by [[IBM]] in 2000 for [[Nintendo]] to use as the [[Central processing unit|CPU]] in their [[Sixth generation of video game consoles|sixth generation game console]], the [[GameCube|Nintendo GameCube]], and later the [[Triforce (arcade system board)|Triforce Arcade Board]].

{{POWER, PowerPC, and Power ISA}}

'''Gekko''' is a superscalar out-of-order [[32-bit]] [[PowerPC]] [[microprocessor]] custom-made by [[IBM]] in 2000 for [[Nintendo]] to use as the [[Central processing unit|CPU]] in their [[Sixth generation of video game consoles|sixth generation game console]], the [[GameCube]], and later the [[Triforce (arcade system board)|Triforce Arcade Board]].


==Development==
==Development==
Gekko's role in the game system was to facilitate game scripting, artificial intelligence, physics and collision detection, custom graphics lighting effects and geometry such as smooth transformations, and moving graphics data through the system.
Gekko's role in the game system was to facilitate game scripting, [[Artificial intelligence in video games|artificial intelligence]], physics and collision detection, custom graphics lighting effects and geometry such as smooth transformations, and moving graphics data through the system.


The project was announced in 1999 when IBM and Nintendo agreed to a one billion dollar contract for a CPU running at approximately 400 MHz. IBM chose to modify their existing [[PowerPC 7xx#PowerPC 750CXe|PowerPC 750CXe]] processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization was to the bus architecture, [[Direct memory access|DMA]], compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects and could burst compressed data directly to the GPU.
The project was announced in 1999 when [[IBM]] and Nintendo agreed to a {{US$|1 billion|long=no}} dollar contract (IBM's largest ever single order)<ref>{{cite magazine |title=DataStream |magazine=[[Edge (magazine)|Edge]] |date=24 November 1999 |issue=79 (December 1999) |page=132 |url=https://retrocdn.net/images/b/bb/Edge_UK_079.pdf#page=134}}</ref> for a CPU running at approximately 400&nbsp;MHz. IBM chose to modify their existing [[PowerPC 7xx#PowerPC 750CXe|PowerPC 750CXe]] processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization was to the bus architecture, [[Direct memory access|DMA]], compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects and could burst compressed data directly to the GPU.{{Citation Needed|date=February 2019}}


IBM's customization led to performance that exceeded Nintendo's specifications.{{Citation needed|date=January 2010}} The Gekko is considered to be the direct ancestor to the [[Broadway (microprocessor)|Broadway]] processor, also designed and manufactured by IBM, that powers the [[Wii]] console.
The Gekko is considered to be the direct ancestor to the [[Broadway (microprocessor)|Broadway]] processor, also designed and manufactured by [[IBM]], that powers the [[Wii]] console.


=== Features===
=== Features===
* Customized [[PowerPC 7xx#PowerPC 750CXe|PowerPC 750CXe]] core
* Customized [[PowerPC 7xx#PowerPC 750CXe|PowerPC 750CXe]] core
* Clockrate - 486 [[Hertz|MHz]]
* Clockrate 486 [[Hertz|MHz]]
* [[Superscalar]] [[Out-of-order execution]]
* [[Superscalar]] [[Out-of-order execution]]
* 4 stages long two-integer [[Arithmetic logic unit|ALU]]s (IU1 and IU2) - 32 bit
* 4 stages long two-integer [[Arithmetic logic unit|ALU]]s (IU1 and IU2) 32 bit
* 7 stages long Floating Point Unit - 64-bit double-precision [[Floating point unit|FPU]], usable as 2×32-bit [[SIMD]] for 1.9 single-precision [[GFLOPS]] performance using the [[Multiply–accumulate operation]]. The SIMD is often found under the denomination "paired singles."
* 7 stages long Floating Point Unit 64-bit double-precision [[Floating point unit|FPU]], usable as 2 × 32-bit [[SIMD]] for 1.9 single-precision [[GFLOPS]] performance using the [[Multiply–accumulate operation]]. The SIMD is often found under the denomination "paired singles."
* Branch Prediction Unit (BPU)
* Branch Prediction Unit (BPU)
* Load-Store Unit (LSU)
* Load-Store Unit (LSU)
Line 49: Line 54:
* Memory Management Unit (MMU)
* Memory Management Unit (MMU)
* Branch Target Instruction Cache (BTIC)
* Branch Target Instruction Cache (BTIC)
* SIMD Instructions - PowerPC750 + roughly 50 new [[SIMD]] instructions, geared toward [[3D graphics]]
* SIMD Instructions PowerPC750 + roughly 50 new [[SIMD]] instructions, geared toward [[3D graphics]]
* Front-side Bus - 64-bit enhanced [[PowerPC 600#60x bus|60x bus]] to [[Graphics processing unit|GPU]]/[[chipset]] at 162&nbsp;MHz clock with 1.3 GB/s peak bandwidth
* Front-side Bus 64-bit enhanced [[PowerPC 600#60x bus|60x bus]] to [[Graphics processing unit|GPU]]/[[chipset]] at 162&nbsp;MHz clock with 1.3 GB/s peak bandwidth
* On-chip Cache - 64 [[Kilobyte|kB]] 8-way [[CPU cache#Associativity|associative]] [[CPU cache|L1 cache]] (32/32 kB instruction/data). 256 KB on-die, 2-way associative L2 cache
* On-chip Cache 64 [[Kilobyte|KB]] 8-way [[CPU cache#Associativity|associative]] [[CPU cache|L1 cache]] (32/32 KB instruction/data). 256 KB on-die, 2-way associative L2 cache
* DMIPS - 1125 ([[dhrystone|dhrystone 2.1]])
* DMIPS 1125 ([[dhrystone|dhrystone 2.1]])
* [[180 nm]] IBM six-layer, copper-wire process. 43&nbsp;mm² [[Die (integrated circuit)|die]]
* [[180 nm]] IBM six-layer, copper-wire process. 43&nbsp;mm² [[Die (integrated circuit)|die]]
* 1.8 [[Volt|V]] for logic and [[I/O]]. 4.9 [[Watt|W]] dissipation
* 1.8 [[Volt|V]] for logic and [[I/O]]. 4.9 [[Watt|W]] dissipation
* 27×27 mm [[Ball grid array|PBGA]] package with 256 contacts
* 27 × 27&nbsp;mm [[Ball grid array|PBGA]] package with 256 contacts
* 6.35 million logic transistors and 18.6 million transistors total
* 6.35 million logic transistors and 18.6 million transistors total


==See also==
==See also==
* [[Broadway (microprocessor)]], the processor in the [[Wii]]
* [[Nintendo GameCube]]
* [[Triforce (arcade system board)]]
* [[PowerPC G3]]
* [[Power Architecture]]
* [[Broadway (microprocessor)]], the processor in the [[Nintendo Wii]]
* MIPS [[R4200#R4300i|R4300]], the processor in the [[Nintendo 64]]
* MIPS [[R4200#R4300i|R4300]], the processor in the [[Nintendo 64]]


== References ==
==References==
{{reflist|30em}}
{{reflist}}
*[http://www-03.ibm.com/press/us/en/pressrelease/2181.wss IBM, Nintendo Announce $1 Billion Technology Agreement]
*{{cite press release |url=http://www-03.ibm.com/press/us/en/pressrelease/2181.wss |title=IBM, Nintendo Announce $1 Billion Technology Agreement |date=May 12, 1999 |publisher=[[IBM]] |archive-url=https://web.archive.org/web/20060821081646/http://www-03.ibm.com/press/us/en/pressrelease/2181.wss |archive-date=2006-08-21 |url-status=dead}}
*[https://www.webcitation.org/66B5UsvoD?url=http://www.hotchips.org/archives/hc13/2_Mon/06ibm-gekko.pdf A PowerPC compatible processor supporting high-performance 3-D graphics]
*[https://old.hotchips.org/wp-content/uploads/hc_archives/hc13/2_Mon/06ibm-gekko.pdf A PowerPC compatible processor supporting high-performance 3-D graphics]


{{GameCube}}
{{Nintendo hardware}}
{{Nintendo hardware}}


Line 76: Line 78:
[[Category:IBM microprocessors]]
[[Category:IBM microprocessors]]
[[Category:Nintendo chips]]
[[Category:Nintendo chips]]
[[Category:PowerPC implementations]]
[[Category:PowerPC microprocessors]]

Latest revision as of 00:36, 16 September 2024

Gekko
IBM Gekko processor
General information
Launched2000
Discontinued2007
Designed byIBM and Nintendo
Common manufacturer
Performance
Max. CPU clock rate486 MHz 
Cache
L1 cache32/32 KB
L2 cache256 KB
Architecture and classification
ApplicationGameCube
Triforce Arcade Board
Technology node180 nm
MicroarchitecturePowerPC G3
Instruction setPowerPC ISA 1.10
Physical specifications
Cores
  • 1
Products, models, variants
Variant
History
PredecessorNEC VR4300
SuccessorBroadway
180nm IBM Gekko CPU in the Gamecube shaved down to expose the silicon die

Gekko is a superscalar out-of-order 32-bit PowerPC microprocessor custom-made by IBM in 2000 for Nintendo to use as the CPU in their sixth generation game console, the GameCube, and later the Triforce Arcade Board.

Development

[edit]

Gekko's role in the game system was to facilitate game scripting, artificial intelligence, physics and collision detection, custom graphics lighting effects and geometry such as smooth transformations, and moving graphics data through the system.

The project was announced in 1999 when IBM and Nintendo agreed to a $1 billion dollar contract (IBM's largest ever single order)[1] for a CPU running at approximately 400 MHz. IBM chose to modify their existing PowerPC 750CXe processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization was to the bus architecture, DMA, compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects and could burst compressed data directly to the GPU.[citation needed]

The Gekko is considered to be the direct ancestor to the Broadway processor, also designed and manufactured by IBM, that powers the Wii console.

Features

[edit]
  • Customized PowerPC 750CXe core
  • Clockrate – 486 MHz
  • Superscalar Out-of-order execution
  • 4 stages long two-integer ALUs (IU1 and IU2) – 32 bit
  • 7 stages long Floating Point Unit – 64-bit double-precision FPU, usable as 2 × 32-bit SIMD for 1.9 single-precision GFLOPS performance using the Multiply–accumulate operation. The SIMD is often found under the denomination "paired singles."
  • Branch Prediction Unit (BPU)
  • Load-Store Unit (LSU)
  • System Register Unit (SRU)
  • Memory Management Unit (MMU)
  • Branch Target Instruction Cache (BTIC)
  • SIMD Instructions – PowerPC750 + roughly 50 new SIMD instructions, geared toward 3D graphics
  • Front-side Bus – 64-bit enhanced 60x bus to GPU/chipset at 162 MHz clock with 1.3 GB/s peak bandwidth
  • On-chip Cache – 64 KB 8-way associative L1 cache (32/32 KB instruction/data). 256 KB on-die, 2-way associative L2 cache
  • DMIPS – 1125 (dhrystone 2.1)
  • 180 nm IBM six-layer, copper-wire process. 43 mm² die
  • 1.8 V for logic and I/O. 4.9 W dissipation
  • 27 × 27 mm PBGA package with 256 contacts
  • 6.35 million logic transistors and 18.6 million transistors total

See also

[edit]

References

[edit]
  1. ^ "DataStream" (PDF). Edge. No. 79 (December 1999). 24 November 1999. p. 132.