User contributions for Juergbi
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A user with 11 edits. Account created on 31 August 2007.
11 April 2022
- 06:3206:32, 11 April 2022 diff hist 0 Belinda Bencic →Singles
1 June 2020
- 19:2719:27, 1 June 2020 diff hist −4 Template:AMD Ryzen 3000 series Undid revision 936138753 by Brouhaha (talk). All Ryzen Threadripper 3000 CPUs have 64 CPU lanes, see https://www.anandtech.com/show/15483/amd-threadripper-3990x-review. Chipset lanes are not included in this table for any of the processors. Tag: Undo
- 19:0819:08, 1 June 2020 diff hist 0 List of Intel CPU microarchitectures Move Cooper Lake from Sunny Cove to Skylake. It is based on the Skylake microarchitecture, not Sunny Cove.
10 May 2020
- 06:1406:14, 10 May 2020 diff hist 0 Epyc Update Max. CPU clock rate (7F32 and 7F52 clock up to 3.9 GHz)
- 06:1106:11, 10 May 2020 diff hist 0 Epyc Correct years for Rome and Milan
11 November 2019
- 13:1213:12, 11 November 2019 diff hist 0 Template:AMD Ryzen 3000 series The Threadripper 3960X/3970X CPUs have 64 lanes. Chipset lanes should not be included in this list. They aren't included for the Ryzen AM4 CPUs either. Tag: Undo
7 January 2019
- 14:2214:22, 7 January 2019 diff hist 0 List of Intel processors Correct thread count for i9-9900k
22 October 2018
- 19:1419:14, 22 October 2018 diff hist −333 Registered memory AMD Threadripper / TR4 mainboards do not support registered memory. While some Intel X299 mainboards initially supported registered memory with Core i9, this was disabled by BIOS / microcode updates.
20 October 2011
- 12:5012:50, 20 October 2011 diff hist +336 Multi-pass compiler Undid revision 454679909 by 117.192.9.75 (talk)
22 June 2008
- 14:1414:14, 22 June 2008 diff hist +344 Talk:Vala (programming language) Add comment regarding hello world sample code
31 August 2007
- 14:0114:01, 31 August 2007 diff hist +13 Vala (programming language) update example to work with Vala 0.1.3
