Wikipedia

2 nm process

This is an old revision of this page, as edited by Pancho507 (talk | contribs) at 21:44, 13 February 2024 (→Background: Add info). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node. As of May 2022, TSMC plans to begin risk 2 nm production at the end of 2024 and mass production in 2025;[1][2] Intel forecasts production in 2024,[3] and Samsung in 2025.[4]

The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.[5]

Process Gate pitch Metal pitch Year
7 nm 60 nm 40 nm 2018
5 nm 51 nm 30 nm 2020
3 nm 48 nm 24 nm 2022
2 nm 45 nm 20 nm 2024
1 nm 42 nm 16 nm 2026


As such, "2 nm" is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.[6][7]

Background

By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of GAAFET:[8] horizontal and vertical nanowires, horizontal nanosheet transistors[9][10] (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors[11][12], complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors[13] and negative-capacitance FET (NC-FET) which uses drastically different materials.[14]

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes;[15] however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.[16] TSMC began research on 2 nm in 2019[17]—expecting to transition from FinFET to GAAFET transistor type.[18] In July 2021, TSMC received governmental approval to build its 2 nm plant. In August 2020, it began building an R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.[19] In September 2020, TSMC confirmed this and stated that it could also install production at Taichung depending on demand.[20] According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023.[21][22] According to Nikkei, the company expects to install production equipment for 2 nm by 2023.[23]

Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027, respectively, and in December 2019 announced plans for 1.4 nm production in 2029.[24]

At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.[25][26]

In May 2021, IBM announced it had produced chips with 2 nm class GAAFET transistors using three silicon layer nanosheets with a gate length of 12 nm.[27][28][29]

In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their 2 nm process node called Intel 20A,[notes 1] with the "A" referring to angstrom, a unit equivalent to 0.1 nanometers.[30] At the same time, they introduced a new process node naming scheme that aligned their product names with similar designations from their main competitors.[31] Intel's 20A node is projected to be their first to move from FinFET to Gate-All-Around transistors (GAAFET); Intel's version is named 'RibbonFET'.[31] Their 2021 roadmap scheduled the Intel 20A node for volume production in 2024 and Intel 18A for 2025.[30][31]

In October 2021, at Samsung Foundry Forum 2021, Samsung announced it would start mass production with its MBCFET (multi-bridge channel FET, Samsung's version of GAAFET) 2 nm process in 2025.[32]

In April 2022, TSMC announced its GAAFET N2 process technology would enter risk production phase at the end of 2024 and production phase in 2025.[1] In July 2022, TSMC announced that its N2 process technology will feature backside power delivery and will offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E.[33]

In July 2022, Samsung made a number of disclosures regarding the company's forthcoming process technology called 2GAP (2nm Gate All-around Production): the process remains on track for 2025 launch into mass production; number of nanosheets will increase from 3 in 3GAP to 4; the company works on several improvements of metallization, namely "single-grain metal" for low-resistance vias and direct-etched metal interconnect planned for 2GAP and beyond.[34]

In August 2022, a consortium of Japanese companies funded a new venture with government support called Rapidus for manufacturing of 2 nm chips. Rapidus signed agreements with imec[35] and IBM[36] in December 2022.

In April 2023, at its Technology Symposium, TSMC introduced two more processes of its 2nm technology platform: N2P featuring backside power delivery and scheduled for 2026 and N2X for high-performance applications. It was also revealed that ARM Cortex-A715 core fabbed on N2 process using high-performance standard library gains 16.4% of speed at iso power, saves 37.2% of power at iso speed, or gains ~10% of speed and saves ~20% of power simultaneously at iso voltage (0.8 V) compared to the core fabbed on N3E using 3-2 fin library.[37]

2 nm process nodes

Samsung[38][34] TSMC Intel
Process name 2GAP N2 N2P N2X 20A 18A
Transistor type MBCFET GAAFET GAAFET GAAFET RibbonFET RibbonFET
Transistor density (MTr/mm2) Un­known 258.7[39] Un­known Un­known Un­known Un­known
SRAM bit-cell size (μm2) Un­known Un­known Un­known Un­known Un­known Un­known
Transistor gate pitch (nm) Un­known Un­known Un­known Un­known Un­known Un­known
Interconnect pitch (nm) Un­known Un­known Un­known Un­known Un­known Un­known
Release status 2025 volume production[32] 2024 H2 risk production
2025 volume production[1] 		2026 production readiness[37] Un­known 2024 H1 risk production[40]
2024 volume production[31][30] 		2024 H2 risk production[40]
2025 production[31][30]

Beyond 2 nm

In July 2021, Intel has planned 18A production for 2025.[30] Intel's February 2022 roadmap added that 18A will deliver 10% improvement in performance per watt compared to Intel 20A and will become manufacturing-ready in 2024 H2.[3]

In December 2021, Vertical-Transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.[41]

In May 2022, imec presented a process technology roadmap which extends the current biannual cadence of node introduction and square-root-of-two node naming rule to 2036. The roadmap ends with process node A2 (for 2 angstroms), named by analogy with TSMC's naming scheme to be introduced by then.[42]

Apart from dimensional scaling of transistor structures and interconnect, innovations forecast by imec are as follows:

  • transistor architecture (forksheet FET, CFET, CFET with atomic (2D material) channel);
  • deployment of high-NA (0.55) EUV tools with the first $400 million tool to be completed at ASML in 2023, and the first production tool to be shipped to Intel in 2025;
  • further reduction of standard cell height (eventually to "less than 4" tracks);
  • back-side power distribution, buried power rails;
  • new materials (ruthenium for metallization (interconnects), graphene, WS2 monolayer for atomic channel);
  • new manufacturing techniques (subtractive metallization, direct metal etch);
  • air gaps to further reduce relative permittivity of intermetal dielectric and, therefore, interconnect capacitance;
  • IC design innovations (2.5D chiplets, 3D interconnect), more advanced EDA tools.

In September 2022, Samsung presented their future business goals, which include an aim to mass-produce 1.4 nm by 2027.[43]

As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).[44]

Notes

  1. ^ Under Intel's previous naming scheme this node was known as 'Intel 5 nm'.[30]

References

  1. ^ a b c "TSMC roadmap update: N3E in 2024, N2 in 2026, major changes incoming". AnandTech. 22 April 2022. Archived from the original on 9 May 2022. Retrieved 9 May 2022.
  2. ^ "TSMC Roadmap Update: 3nm in Q1 2023, 3nm Enhanced in 2024, 2nm in 2025". AnandTech. 18 October 2021. Archived from the original on 23 March 2022. Retrieved 23 March 2022.
  3. ^ a b "Intel Technology Roadmaps and Milestones". Intel. 17 February 2022. Archived from the original on 16 July 2022. Retrieved 15 March 2022.
  4. ^ "Samsung Foundry: 2nm Silicon in 2025". AnandTech. 6 October 2021. Archived from the original on 23 March 2022. Retrieved 23 March 2022.
  5. ^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
  6. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". Archived from the original on 17 June 2020. Retrieved 20 April 2020.
  7. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
  8. ^ https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/
  9. ^ https://semiengineering.com/whats-different-about-next-gen-transistors/
  10. ^ https://spectrum.ieee.org/amp/intels-stacked-nanosheet-transistors-could-be-the-next-step-in-moores-law-2652903505
  11. ^ https://spectrum.ieee.org/amp/nanowire-transistors-could-keep-moores-law-alive-2650269271
  12. ^ https://physicsworld.com/a/nanowires-give-vertical-transistors-a-boost/
  13. ^ https://semiengineering.com/whats-after-finfets/
  14. ^ https://semiengineering.com/transistor-options-beyond-3nm/
  15. ^ Patterson, Alan (12 September 2018), "TSMC: Chip Scaling Could Accelerate", www.eetimes.com, archived from the original on 24 September 2018, retrieved 23 September 2020
  16. ^ Merritt, Rick (4 March 2019), "SPIE Conference Predicts Bumpy Chip Roadmap", www.eetasia.com, archived from the original on 27 June 2019, retrieved 23 September 2020
  17. ^ Zafar, Ramish (12 June 2019), TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report, archived from the original on 7 November 2020, retrieved 23 September 2020
  18. ^ "Highlights of the day: TSMC reportedly adopts GAA transistors for 2nm chips", www.digitimes.com, 21 September 2020, archived from the original on 23 October 2020, retrieved 23 September 2020
  19. ^ Wang, Lisa (26 August 2020), "TSMC developing 2nm tech at new R&D center", taipeitimes.com, archived from the original on 24 January 2021, retrieved 23 September 2020
  20. ^ Chien-Chung, Chang; Huang, Frances (23 September 2020), "TSMC to build 2nm wafer plant in Hsinchu", focustaiwan.tw, archived from the original on 25 October 2020, retrieved 23 September 2020
  21. ^ Udin, Efe (23 September 2020), "TSMC 2NM PROCESS MAKES A SIGNIFICANT BREAKTHROUGH", www.gizchina.com, archived from the original on 19 October 2021, retrieved 24 September 2021
  22. ^ 台积电2nm工艺重大突破！2023年风险试产良率或达90% (in Chinese), 22 September 2020, archived from the original on 24 September 2021, retrieved 24 September 2021
  23. ^ "Taiwan gives TSMC green light for most advanced chip plant". Nikkei Asia. Archived from the original on 4 November 2021. Retrieved 24 August 2021.
  24. ^ Cutress, Ian, "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm", www.anandtech.com, archived from the original on 12 January 2021, retrieved 23 September 2020
  25. ^ Dahad, Nitin (9 December 2020), "EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology", www.eetimes.eu, archived from the original on 10 January 2021, retrieved 9 January 2021
  26. ^ Joint declaration on processors and semiconductor technologies, EU, 7 December 2020, archived from the original on 11 January 2021, retrieved 9 January 2021
  27. ^ Nellis, Stephen (6 May 2021), "IBM unveils 2-nanometer chip technology for faster computing", Reuters, archived from the original on 7 May 2021, retrieved 6 May 2021
  28. ^ Johnson, Dexter (6 May 2021), "IBM Introduces the World's First 2-nm Node Chip", IEEE Spectrum, archived from the original on 7 May 2021, retrieved 7 May 2021
  29. ^ 12 nm gate length is the dimension defined by the IRDS 2020 to be associated with the "1.5 nm" process node: [1] Archived 24 June 2021 at the Wayback Machine
  30. ^ a b c d e f Cutress, Dr Ian (26 July 2021). "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". www.anandtech.com. Archived from the original on 3 November 2021. Retrieved 27 July 2021.
  31. ^ a b c d e Santo, Brian (27 July 2021), "Intel Charts Manufacturing Course to 2025", www.eetimes.com, archived from the original on 19 August 2021, retrieved 11 August 2021
  32. ^ a b "Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices". Samsung. 7 October 2021. Archived from the original on 8 April 2022. Retrieved 9 May 2022.
  33. ^ "TSMC Q2 2022 Earnings Call" (PDF). TSMC. 14 July 2022. Archived (PDF) from the original on 15 July 2022. Retrieved 22 July 2022.
  34. ^ a b "Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements". WikiChip Fuse. 5 July 2022.
  35. ^ Manners, David (16 December 2022). "Imec and Rapidus sign up for 2nm". Electronics Weekly.
  36. ^ Humphries, Matthew (13 December 2022). "Japan to Manufacture 2nm Chips With a Little Help From IBM". PCMAG.
  37. ^ a b "TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To The Roadmap". AnandTech. 26 April 2023.
  38. ^ "Samsung Foundry: 2nm Silicon in 2025". AnandTech. 6 October 2021.
  39. ^ "TSMC Q2 2022 Earnings Call" (PDF). TSMC. 14 July 2022. Archived (PDF) from the original on 15 July 2022. Retrieved 22 July 2022.
  40. ^ a b https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/2
  41. ^ Jagannathan, H.; et al. (2021). "Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices". 2021 IEEE International Electron Devices Meeting (IEDM). pp. 26.1.1–26.1.4. doi:10.1109/IEDM19574.2021.9720561. ISBN 978-1-6654-2572-8. S2CID 247321213.
  42. ^ "Imec Presents Sub-1nm Process and Transistor Roadmap Until 2036". Tom's Hardware. 21 May 2022.
  43. ^ "Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022". Samsung Global Newsroom. 4 October 2022.
  44. ^ https://spectrum.ieee.org/cfet-intel-samsung-tsmc

Further reading

Preceded by
3 nm (FinFET/GAAFET) 		MOSFET semiconductor device fabrication process Succeeded by
unknown
Retrieved from "https://en.wikipedia.org/w/index.php?title=2_nm_process&oldid=1207060671"