Registered memory: Difference between revisions

'''Registered (Buffered) DIMM (R-DIMM)''' modules insert a [[Digital buffer|buffer]] between the pins of the command and address buses on the DIMM and the memory chips. A high-capacity DIMM might have numerous memory chips, each of which must receive the memory address, and their combined [[Parasitic capacitance|input capacitance]] limits the speed at which the memory bus can operate. By redistributing the command and address signals within the R-DIMM, this allows more chips to be connected to the memory bus.<ref name="anandtech">{{cite web
| url = http://www.anandtech.com/show/6068/lrdimms-rdimms-supermicros-latest-twin/2
| title = LRDIMMs, RDIMMs, and Supermicro's Latest Twin
| date = 2012-08-03 | accessdate = 2014-09-09
| author = Johan De Gelas | publisher = [[AnandTech]]
}}</ref> The cost is increased [[memory latency]], as a result of one{{cn}} additional clock cycle required for the address to traverse the additional buffer. Early registered RAM modules were physically incompatible with unregistered RAM modules, but the two variants of SDRAM R-DIMMs are mechanically interchangeable, and some motherboards may support both types.

'''Load Reduced DIMM (LR-DIMM)''' modules are similar to R-DIMMs, but add a buffer to the data lines as well. In other words, LR-DIMMs buffer both control and data lines while keeping the parallel nature of all signals. As a result, LR-DIMMs provides large overall maximum memory capacities, while avoiding the performance and power consumption problems of FB-DIMMs, induced by the required conversion between serial and parallel signal forms.<ref name="anandtech" /><ref name="lrdimm">{{cite web