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{{use dmy dates|date=March 2022}}
In [[semiconductor manufacturing]], the '''2 nm process''' is the next [[MOSFET]] (metal–oxide–semiconductor field-effect transistor) [[die shrink]] after the [[
The term "2 [[Nanometre|nanometer]]", or alternatively "20 [[angstrom]]" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the [[International Roadmap for Devices and Systems]] published by the [[Institute of Electrical and Electronics Engineers]] (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.<ref>{{Citation |url=https://irds.ieee.org/editions/2021/more-moore |title=INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore |year=2021 |publisher=IEEE |page=7 |access-date=7 August 2022 |archive-date=7 August 2022 |archive-url=https://web.archive.org/web/20220807181530/https://irds.ieee.org/editions/2021/more-moore }}</ref>
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In September 2024, Intel announced they would no longer be moving forward with their 20A process node, instead focusing on the development of 18A. Intel projected that avoiding ramping production of 20A could save over half a billion dollars. Intel noted that they'd successfully implemented [[RibbonFET]] gate-all-around architecture and [[PowerVia]] [[backside power delivery]] in their 20A process, accelerating 18A development. Intel's
== 2 nm process nodes ==
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| {{Unknown}} || 0.021<ref name="ISSCC2025_INTEL">[https://submissions.mirasmart.com/ISSCC2025/PDF/ISSCC2025AdvanceProgram.pdf A 0.021μm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery (19 Feb 2025)]</ref>
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! Transistor gate pitch (nm)
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Apart from the expected shrinking of transistor structures and interconnects, innovations forecasted by [[IMEC|imec]] were as follows:{{and then what|date=February 2024}}
* transistor architecture (forksheet FET, CFET, CFET with atomic (2D material) channel);
* deployment of high-[[Numerical aperture|NA]] (0.55) [[Extreme ultraviolet lithography|EUV]] tools with the first $400 million tool to be completed at [[ASML Holding|ASML]] in 2023, and the first production tool
* further reduction of standard cell height (eventually to "less than 4" tracks);
* back-side power distribution, buried power rails;
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In September 2022, [[Samsung Electronics|Samsung]] presented their future business goals, which at that time included an aim to mass-produce 1.4 nm by 2027.<ref>{{cite web|url=https://news.samsung.com/global/samsung-electronics-unveils-plans-for-1-4nm-process-technology-and-investment-for-production-capacity-at-samsung-foundry-forum-2022|title=Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022|website=Samsung Global Newsroom|date=2022-10-04}}</ref>
As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).<ref>{{cite web | url=https://spectrum.ieee.org/cfet-intel-samsung-tsmc | title=Intel, Samsung, and TSMC Demo 3D-Stacked Transistors - IEEE Spectrum
==Notes==
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