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{{Semiconductor manufacturing processes}}
{{use dmy dates|date=March 2022}}
In [[semiconductor manufacturing]], the '''"2 nm process"''' is the next [[MOSFET]] (metal–oxide–semiconductor field-effect transistor) [[die shrink]] after the [[3 nm process|"3 nm" process]] node.▼
▲In [[semiconductor manufacturing]], the '''
The term "2 [[Nanometre|nanometer]]" or alternatively "20 [[angstrom]]" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the [[International Roadmap for Devices and Systems]] published by the [[Institute of Electrical and Electronics Engineers]] (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.<ref>{{Citation |url=https://irds.ieee.org/editions/2021/more-moore |title=INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore |year=2021 |publisher=IEEE |page=7 |access-date=7 August 2022 |archive-date=7 August 2022 |archive-url=https://web.archive.org/web/20220807181530/https://irds.ieee.org/editions/2021/more-moore }}</ref> ▼
▲The term "2 [[Nanometre|nanometer]]", or alternatively "20 [[angstrom]]" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the [[International Roadmap for Devices and Systems]] published by the [[Institute of Electrical and Electronics Engineers]] (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.<ref>{{Citation |url=https://irds.ieee.org/editions/2021/more-moore |title=INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore |year=2021 |publisher=IEEE |page=7 |access-date=7 August 2022 |archive-date=7 August 2022 |archive-url=https://web.archive.org/web/20220807181530/https://irds.ieee.org/editions/2021/more-moore }}</ref>
{| class="wikitable"
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| [[5 nm process|5 nm]] || 51 nm || 30 nm || 2020
|-
| [[3 nm process|3 nm]] || 48 nm || 24 nm || 2022
|-
| 2 nm || 45 nm || 20 nm || 2025
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|}
As such,
[[TSMC]] began risk production of its 2 nm process in July 2024, with mass production planned for the second half of 2025,<ref name=tsmc_rm_2022 /><ref>{{Cite web |last=Salman |first=Ali |date=2024-07-09 |title=Apple Supplier TSMC Will Begin Trial Production Of 2nm Chips Next Week, Aiming To Secure A Stable Yield Before Mass Production |url=https://wccftech.com/tsmc-to-begin-trial-production-of-2nm-chips-next-week/ |access-date=2024-09-10 |website=Wccftech |language=en-US}}</ref> and [[Samsung]] plans to start production in 2025.<ref>{{Cite web |last=Shilov |first=Anton |title=Samsung Foundry Unveils Updated Roadmap: BSPDN and 2nm Evolution Through 2027 |url=https://www.anandtech.com/show/21444/samsung-foundry-unveils-updated-roadmap-2nm-evolution-through-2027 |access-date=2024-09-10 |website=www.anandtech.com}}</ref> [[Intel]] initially forecasted production in 2024 but scrapped its 2 nm node in favor of the smaller 18 angstrom (18A) node.<ref name=":0">{{Cite web |last=Alcorn |first=Paul |date=2024-09-04 |title=Intel announces cancellation of 20A process node for Arrow Lake, goes with external nodes instead, likely TSMC [Updated] |url=https://www.tomshardware.com/pc-components/cpus/intel-announces-cancellation-of-20a-process-node-for-arrow-lake-goes-with-external-nodes-instead-likely-tsmc |access-date=2024-09-10 |website=Tom's Hardware |language=en}}</ref>
==Background==
By 2018, a number of transistor architectures had been proposed for the eventual replacement of [[FinFET]], most of which were based on the concept of [[GAAFET]]:<ref>{{cite web | url=https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/ | title=The Increasingly Uneven Race to 3nm/2nm | date=24 May 2021 }}</ref> horizontal and vertical nanowires, horizontal nanosheet transistors<ref>{{cite web | url=https://semiengineering.com/whats-different-about-next-gen-transistors/ | title=What's Different About Next-Gen Transistors | date=20 October 2022 }}</ref><ref>{{cite web | url=https://spectrum.ieee.org/amp/intels-stacked-nanosheet-transistors-could-be-the-next-step-in-moores-law-2652903505 | title=Intel's Stacked Nanosheet Transistors Could be the Next Step in Moore's Law }}</ref> (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,<ref>{{cite web | url=https://spectrum.ieee.org/amp/nanowire-transistors-could-keep-moores-law-alive-2650269271 | title=Nanowire Transistors Could Keep Moore's Law Alive }}</ref><ref>{{cite web | url=https://physicsworld.com/a/nanowires-give-vertical-transistors-a-boost/ | title=Nanowires give vertical transistors a boost | date=2 August 2012 }}</ref> complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors<ref>{{cite web | url=https://semiengineering.com/whats-after-finfets/ | title=What's After FinFETs? | date=24 July 2017 }}</ref> and negative-capacitance FET (NC-FET) which uses drastically different materials.<ref>{{cite web | url=https://semiengineering.com/transistor-options-beyond-3nm/ | title=Transistor Options Beyond 3nm | date=15 February 2018 }}</ref>
In late 2018, [[TSMC]] chairman Mark Liu predicted chip scaling would continue to
[[Intel]]'s 2019 roadmap scheduled potentially equivalent
At the end of 2020, seventeen [[European Union]] countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as
In May 2021, [[IBM]] announced it had produced chips with
In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their
In October 2021, at Samsung Foundry Forum 2021, Samsung announced it would start mass production with its MBCFET (multi-bridge channel FET, Samsung's version of GAAFET)
In April 2022, TSMC announced its GAAFET
In July 2022, Samsung made a number of disclosures regarding the company's previously forthcoming process technology called "2GAP" (
|url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/
|title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements
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}}</ref>{{and then what|date=February 2024}}
In August 2022, a consortium of Japanese companies funded a new venture with government support called [[Rapidus]] for manufacturing of
In April 2023, at its Technology Symposium, TSMC introduced two more processes of its
{{cite web
|url=https://www.anandtech.com/show/18832/tsmc-outlines-2nm-plans-n2p-brings-backside-power-delivery-in-2026-n2x-added-to-roadmap
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}}</ref>
In September 2024, Intel announced they would no longer be moving forward with their 20A process node, instead focusing on the development of 18A. Intel projected that avoiding ramping production of 20A could save over half a billion dollars. Intel noted that they'd successfully implemented [[RibbonFET]] gate-all-around architecture and [[PowerVia]] [[backside power delivery]] in their 20A process, accelerating 18A development. Intel's [[Arrow Lake (microprocessor)|Arrow Lake]] family of processors, which were meant to use Intel 20A, will instead have dies sourced from "external partners" and packaged by Intel.<ref name=":0" /><ref>{{Cite web |last=Sell |first=ben |date=2024-09-04 |title=Continued Momentum for Intel 18A |url=https://www.intel.com/content/www/us/en/newsroom/opinion/continued-momentum-intel-18a.html#gs.efsu7s |access-date=2024-09-11 |website=Intel |language=en}}</ref>
== "2 nm" process nodes ==▼
{| class="wikitable" style="text-align:center"
!
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|website=AnandTech
|date=2021-10-06
}}</ref><ref name=sams_wikichip /><ref>{{cite web | url=https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year
! colspan="3" | [[TSMC]]
! colspan="2" | [[Intel]]
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| {{Unknown}} || {{Unknown}} || {{Unknown}} || {{Unknown}}
| {{Unknown}} || {{Unknown}} || {{Unknown}}
| {{Unknown}} || 0.021<ref name="ISSCC2025_INTEL">[https://submissions.mirasmart.com/ISSCC2025/PDF/ISSCC2025AdvanceProgram.pdf A 0.021μm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery (19 Feb 2025)]</ref>
|-
! Transistor gate pitch (nm)
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! Release status
| {{no|2025 volume production}}<ref name=":1" /> || {{no|2026 volume production}} || {{no|2026 volume production}} || {{no|2027 volume production}}
| {{no|2025 risk production<br />2025 H2 volume production}}<ref name="tsmc2024">{{cite web | url=https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations
| {{no|2024 H1 risk production}}<ref name="Intel2023">{{cite web | url=https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/2 | title=Intel Unveils Meteor Lake Architecture: Intel 4 Heralds the Disaggregated Future of Mobile CPUs }}</ref><br />2024 volume production<ref name="ee20a" /><ref name=intelroadmap /><br />Canceled 2024<ref name="Intel18AShift">{{cite web | url=https://www.intel.com/content/www/us/en/newsroom/opinion/continued-momentum-intel-18a.html | title=Continued Momentum for Intel 18A |date=September 4, 2024 }}</ref> || {{no|2024 H2 risk production}}<ref name=Intel2023 /><br />2025 H1 production<ref name="ee20a" /><ref name=intelroadmap /><ref>{{Cite web|url=https://www.techpowerup.com/321900/intel-reports-first-quarter-2024-financial-results|title=Intel
|-
|}
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In July 2021, [[Intel]] reported that they planned
In December 2021, Vertical-Transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.<ref>{{cite book | chapter-url=https://ieeexplore.ieee.org/document/9720561 | doi=10.1109/IEDM19574.2021.9720561 | s2cid=247321213 | chapter=Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices | title=2021 IEEE International Electron Devices Meeting (IEDM) | year=2021 | last1=Jagannathan | first1=H. | last2=Anderson | first2=B. | last3=Sohn | first3=C-W. | last4=Tsutsui | first4=G. | last5=Strane | first5=J. | last6=Xie | first6=R. | last7=Fan | first7=S. | last8=Kim | first8=K-I. | last9=Song | first9=S. | last10=Sieg | first10=S. | last11=Seshadri | first11=I. | last12=Mochizuki | first12=S. | last13=Wang | first13=J. | last14=Rahman | first14=A. | last15=Cheon | first15=K-Y. | last16=Hwang | first16=I. | last17=Demarest | first17=J. | last18=Do | first18=J. | last19=Fullam | first19=J. | last20=Jo | first20=G. | last21=Hong | first21=B. | last22=Jung | first22=Y. | last23=Kim | first23=M. | last24=Kim | first24=S. | last25=Lallement | first25=R. | last26=Levin | first26=T. | last27=Li | first27=J. | last28=Miller | first28=E. | last29=Montanini | first29=P. | last30=Pujari | first30=R. | pages=26.1.1–26.1.4 | isbn=978-1-6654-2572-8 | display-authors=1 }}</ref>
In May 2022, [[IMEC|imec]] presented a process technology roadmap which extends the current biannual cadence of node introduction and square-root-of-two node naming rule to 2036. The roadmap ends with process node "A2" (
Apart from
* transistor architecture (forksheet FET, CFET, CFET with atomic (2D material) channel);
* deployment of high-[[Numerical aperture|NA]] (0.55) [[Extreme ultraviolet lithography|EUV]] tools with the first $400 million tool to be completed at [[ASML Holding|ASML]] in 2023, and the first production tool
* further reduction of standard cell height (eventually to "less than 4" tracks);
* back-side power distribution, buried power rails;
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* IC design innovations (2.5D chiplets, 3D interconnect), more advanced EDA tools.
In September 2022, [[Samsung Electronics|Samsung]] presented their future business goals, which at that time included an aim to mass-produce
As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).<ref>{{cite web | url=https://spectrum.ieee.org/cfet-intel-samsung-tsmc | title=Intel, Samsung, and TSMC Demo 3D-Stacked Transistors - IEEE Spectrum
==Notes==
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