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ORCIDNaren Narasimhan
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2000 – 2009
- 2009
[c9]Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik:
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. CAV 2009: 414-429- 2004
- [c8]William N. N. Hung, Naren Narasimhan:
Reference model based RTL verification: an integrated approach. HLDVT 2004: 9-13 - 2002
- [c7]Roope Kaivola, Naren Narasimhan:
Formal Verification of the Pentium ® 4 Floating-Point Multiplier. DATE 2002: 20-27 - 2001
- [j1]Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri
:
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. Formal Methods Syst. Des. 19(3): 237-273 (2001) - [c6]Roope Kaivola, Naren Narasimhan:
Formal verification of the Pentium(R) 4 multiplier. HLDVT 2001: 115-120
1990 – 1999
- 1998
- [c5]Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri:
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis. ICCD 1998: 392-399 - [c4]Naren Narasimhan, Ranga Vemuri:
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. TPHOLs 1998: 367-386 - 1996
- [c3]Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri:
Rapid Prototyping of Reconfigurable Coprocessors. ASAP 1996: 303-312 - [c2]Naren Narasimhan, Ranga Vemuri:
Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. FMCAD 1996: 327-345 - [c1]Naren Narasimhan, Ranga Vemuri, Jay Roy:
Synchronous Controller Models for Synthesis from Communicating VHDL Processes. VLSI Design 1996: 198-204
Coauthor Index
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