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ORCIDJae Hoon Shim
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2020 – today
- 2023
[j10]Jaejin Kim
, Gunmo Koo, Seongmin Lee, Jae Hoon Shim, Kunhee Cho:
An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4975-4985 (2023)- [c7]Dong-Jick Min, Jun-Gi Lee, Kunhee Cho, Jae Hoon Shim:
An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time. ISCAS 2023: 1-5 - 2021
- [c6]Jae Hoon Shim, Hochang Rhee, Yeong Il Jang, Geonsu Lee, Seyun Kim, Nam Ik Cho:
Lossless Image Compression Based on Image Decomposition and Progressive Prediction Using Convolutional Neural Networks. APSIPA ASC 2021: 158-163 - [c5]Geonsu Lee, Hochang Rhee, Jae Hoon Shim, Hyung Il Koo, Nam Ik Cho:
Network Intrusion Detection with Improved Feature Representation. APSIPA ASC 2021: 2049-2054 - [c4]Dong-Jick Min, Jae Hoon Shim:
A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs. ISCAS 2021: 1-5
2010 – 2019
- 2018
- [j9]Changho Yoon, Jae Hoon Shim, Byungin Moon, Joonho Kong:
3D die-stacked DRAM thermal management via task allocation and core pipeline control. IEICE Electron. Express 15(3): 20171253 (2018) - [j8]Seung-Ho Ok, Jae Hoon Shim, Byungin Moon:
Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors. J. Supercomput. 74(12): 6665-6690 (2018) - [c3]Dong-Jick Min, Sun Youl Choi, Jae Hoon Shim:
A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector. ICECS 2018: 817-820 - 2017
- [j7]Seung-Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon:
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors. Sensors 17(2): 426 (2017) - 2010
- [j6]Sangjin Byun, Jae Hoon Shim:
Charge Pump circuit with wide range digital leakage current mismatch compensator. IEICE Electron. Express 7(23): 1709-1713 (2010)
2000 – 2009
- 2006
- [j5]Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector. IEEE J. Solid State Circuits 41(11): 2566-2576 (2006) - [c2]Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector. ISSCC 2006: 1324-1333 - 2005
- [j4]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits 40(4): 918-925 (2005) - [j3]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits 40(11): 2339 (2005) - [j2]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(5): 885-893 (2005) - 2003
- [c1]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) 2003: 1025-1028 - 2001
- [j1]Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim:
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. IEEE J. Solid State Circuits 36(4): 648-657 (2001)
Coauthor Index
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