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ORCIDH. Narayanan
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2020 – today
- 2023
[i4]H. Narayanan:
On composition and decomposition operations for vector spaces, graphs and matroids. CoRR abs/2305.16354 (2023)- 2021
- [i3]H. Narayanan:
Implicit Linear Algebra and Basic Circuit Theory II: port behaviour of rigid multiports. CoRR abs/2103.04592 (2021) - [i2]H. Narayanan, Hariharan Narayanan:
On Thevenin-Norton and Maximum power transfer theorems. CoRR abs/2104.05202 (2021) - 2020
- [i1]H. Narayanan, Hariharan Narayanan:
Implicit Linear Algebra and Basic Circuit Theory. CoRR abs/2005.00838 (2020)
2010 – 2019
- 2016
- [c26]Vinay B. Y. Kumar
, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar:
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. VLSID 2016: 409-414 - 2013
- [j14]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Solution of PDEs-electrically coupled systems with electrical analogy. Integr. 46(4): 427-440 (2013) - [c25]Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar:
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields. PECCS 2013: 195-201 - [c24]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. VLSI Design 2013: 356-361 - 2012
- [c23]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Two Graph Based Circuit Simulator for PDE-Electrical Analogy. VLSI Design 2012: 400-405 - 2011
- [j13]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Solution of Partial Differential Equations by electrical analogy. J. Comput. Sci. 2(1): 18-30 (2011) - [j12]Gautam Hazari, H. Narayanan:
On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1861-1873 (2011) - 2010
- [j11]Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. Int. J. Parallel Program. 38(3-4): 322-338 (2010) - [c22]Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Large Scale VLSI Circuit Simulation Using Point Relaxation. CSC 2010: 343-347
2000 – 2009
- 2009
- [c21]V. Siva Sankar, H. Narayanan, Sachin B. Patkar:
Exploiting Hybrid Analysis in Solving Electrical Networks. VLSI Design 2009: 206-211 - [c20]Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. VLSI Design 2009: 341-346 - 2007
- [c19]Gaurav Trivedi, H. Narayanan:
Application of Fast DC Analysis to Partitioning Hypergraphs. ISCAS 2007: 3407-3410 - [c18]Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Parallelization of DC Analysis through Multiport Decomposition. VLSI Design 2007: 863-868 - [c17]Gaurav Trivedi, Sumit Punglia, H. Narayanan:
Application of DC Analyzer to Combinatorial Optimization Problems. VLSI Design 2007: 869-874 - 2006
- [c16]Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Fast DC Analysis and Its Application to Combinatorial Optimization Problems. VLSI Design 2006: 695-700 - 2004
- [c15]H. Narayanan:
Mathematical programming and resistor transformer diode networks. ICECS 2004: 69-72 - 2003
- [j10]Madhav P. Desai, H. Narayanan, Sachin B. Patkar:
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. Discret. Appl. Math. 131(2): 299-310 (2003) - [j9]H. Narayanan:
A note on the minimization of symmetric and general submodular functions. Discret. Appl. Math. 131(2): 513-522 (2003) - [j8]Sachin B. Patkar, H. Narayanan:
Improving graph partitions using submodular functions. Discret. Appl. Math. 131(2): 535-553 (2003) - [j7]Sachin B. Patkar, H. Narayanan:
Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition. J. Comb. Optim. 7(1): 45-68 (2003) - [c14]Sachin B. Patkar, H. Narayanan:
An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. VLSI Design 2003: 64-69 - 2002
- [j6]Harish K. Pillai, H. Narayanan:
On Duality of Behavioural Systems. Multidimens. Syst. Signal Process. 13(4): 357-383 (2002) - [j5]H. Narayanan:
Some applications of an Implicit Duality Theorem to connections of structures of special types including Dirac and reciprocal structures. Syst. Control. Lett. 45(2): 87-95 (2002) - [c13]M. V. Atre, P. S. Subramanian, H. Narayanan:
Mathematical Methods in VLSI (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 18-19 - 2001
- [j4]Sachin B. Patkar, H. Narayanan:
A note on optimal covering augmentation for graphic polymatroids. Inf. Process. Lett. 79(6): 285-290 (2001) - [c12]Shabbir H. Batterywala, H. Narayanan:
Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. VLSI Design 2001: 500- - 2000
- [c11]Sachin B. Patkar, H. Narayanan:
Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and Its Connections with Principal Partition. FSTTCS 2000: 94-105
1990 – 1999
- 1999
- [c10]Rupesh S. Shelar, Madhav P. Desai, H. Narayanan:
Decomposition of Finite State Machines for Area, Delay Minimization. ICCD 1999: 620-625 - [c9]Shabbir H. Batterywala, H. Narayanan:
Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. VLSI Design 1999: 169-174 - [c8]B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai:
A State Assignment Scheme Targeting Performance and Area. VLSI Design 1999: 378-383 - 1997
- [c7]Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan:
A New Partitioning Strategy Based on Supermodular Functions. VLSI Design 1997: 32-37 - 1996
- [j3]H. Narayanan, Subir K. Roy, Sachin B. Patkar:
Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach. J. Algorithms 21(2): 306-330 (1996) - 1994
- [j2]H. Narayanan, Huzur Saran, Vijay V. Vazirani:
Randomized Parallel Algorithms for Matroid Union and Intersection, With Applications to Arboresences and Edge-Disjoint Spanning Trees. SIAM J. Comput. 23(2): 387-397 (1994) - [c6]H. Narayanan, Subir K. Roy, Sachin B. Patkar:
Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach. MFCS 1994: 525-535 - 1993
- [c5]Subir K. Roy, H. Narayanan:
Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine. ISCAS 1993: 2564-2567 - 1992
- [c4]Sachin B. Patkar, H. Narayanan:
Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut. FSTTCS 1992: 265-278 - [c3]Sachin B. Patkar, H. Narayanan:
Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity. ISAAC 1992: 41-50 - [c2]H. Narayanan, Huzur Saran, Vijay V. Vazirani:
Randomized Parallel Algorithms for Matroid Union and Intersection, with Applications to Arboresences and Edge-Disjoint Spanning Trees. SODA 1992: 357-366 - 1991
- [c1]Sachin B. Patkar, H. Narayanan:
A Fast Algorithm for the Principle Partition of a Graph. FSTTCS 1991: 288-306 - 1990
- [j1]H. Narayanan:
On the minimum hybrid rank of a graph relative to a partition of its edges and its application to electrical network analysis. Int. J. Circuit Theory Appl. 18(3): 269-288 (1990)
Coauthor Index
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