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First test results of the CHIPIX65 asynchronous front-end connected to a 3D sensor
/ Gaioni, L. (Universita di Bergamo) ; De Canio, F. (Universita di Pavia, INFN Pavia) ; Manghisoni, M. (Universita di Bergamo, INFN Pavia) ; Ratti, L. (Universita di Pavia, INFN Pavia) ; Re, V. (Universita di Bergamo, INFN Pavia) ; Sonzogni, M. (Universita di Bergamo, INFN Pavia) ; Traversi, G. (Universita di Bergamo, INFN Pavia)
This work reports on the main results from the experimental characterization of the asynchronous analog front-end integrated in a 65 nm CMOS mixed-signal chip for the readout of high granularity silicon pixel sensors at the high-luminosity upgrades of the
ATLAS and CMS experiments. Such a mixed-signal chip has been designed and submitted in the framework of the CHIPIX65 project, funded by the Italian Institute of Nuclear Physics for the development of an advanced pixel chip in a 65 nm CMOS technology. [...]
AIDA-2020-PUB-2020-010.-
Geneva : CERN, 2019
- Published in : Nucl. Instrum. Methods Phys. Res., A 936 (2019) 319-320
Fulltext: PDF;
In : Frontier Detectors for Frontier Physics: XIV Pisa Meeting on Advanced Detectors, La Biodola, Isola D'elba, Italy, 27 May - 2 Jun 2018, pp.319-320
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Analog front-end characterization of the RD53A chip
/ Emriskova, Natalia (CERN)
/CMS Collaboration
For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel detector readout chip, with a 50 μm × 50 μm pixel size, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, is now available. [...]
CMS-CR-2019-202.-
Geneva : CERN, 2020 - 6 p.
- Published in : PoS TWEPP2019 (2020) 021
Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.021
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Design of analog front-ends for the RD53 demonstrator chip
/ Gaioni, L (Bergamo U. ; INFN, Pavia) ; De Canio, F (Bergamo U. ; INFN, Pavia) ; Nodari, B (Bergamo U. ; INFN, Pavia) ; Manghisoni, M (Bergamo U. ; INFN, Pavia) ; Re, V (Bergamo U. ; INFN, Pavia) ; Traversi, G (Bergamo U. ; INFN, Pavia) ; Barbero, M B (Marseille, CPPM) ; Fougeron, D (Marseille, CPPM) ; Gensolen, F (Marseille, CPPM) ; Godiot, S (Marseille, CPPM) et al.
The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. [...]
SISSA, 2017 - 14 p.
- Published in : PoS Vertex 2016 (2017) 036
Fulltext: PDF; External link: PoS server
In : VERTEX 2016, La Biodola, Italy, 25 - 30 Sep 2016, pp.036
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Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 024
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
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Serial powering and high hit rate efficiency measurement for the Phase 2 Upgrade of the CMS Pixel Detector.
/ Ruini, Daniele (Zurich, ETH)
A serially powered pixel detector is the baseline choice for the High Luminosity upgrade of the inner tracker of the CMS experiment. A serial power distribution scheme, compared to parallel powering, requires less cable mass, offers higher power efficiency and is less susceptible to voltage transients. [...]
CMS-CR-2019-009.-
Geneva : CERN, 2019 - 10 p.
- Published in : JINST 14 (2019) C10024
Fulltext: PDF;
In : International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2018), Taipei, Taiwan, 10 - 14 Dec 2018, pp.C10024
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Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC
/ Demaria, N (INFN, Turin) ; Barbero, M B (Marseille, CPPM) ; Fougeron, D (Marseille, CPPM) ; Gensolen, F (Marseille, CPPM) ; Godiot, S (Marseille, CPPM) ; Menouni, M (Marseille, CPPM) ; Pangaud, P (Marseille, CPPM) ; Rozanov, A (Marseille, CPPM) ; Wang, A (Marseille, CPPM) ; Bomben, M (Paris U., VI-VII) et al.
/RD53
This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. [...]
FERMILAB-CONF-16-622-PPD.-
2016
- Published in : JINST 11 (2016) C12058
IOP Open Access article: PDF;
In : International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2016), Sestri Levante, Italy, 5 - 9 Sep 2016, pp.C12058
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A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
/ Paternò, Andrea (INFN, Turin ; Turin Polytechnic) ; Pacher, L (Turin U. ; INFN, Turin) ; Monteil, E (Turin U. ; INFN, Turin) ; Loddo, F (INFN, Bari) ; Demaria, N (INFN, Turin) ; Gaioni, L (INFN, Pavia ; Bergamo U., Ingengneria Dept.) ; Canio, F De (INFN, Pavia ; Pavia U.) ; Traversi, G (INFN, Pavia ; Bergamo U., Ingengneria Dept.) ; Re, V (INFN, Pavia ; Bergamo U., Ingengneria Dept.) ; Ratti, L (INFN, Pavia ; Pavia U.) et al.
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. [...]
2017 - 12 p.
- Published in : JINST 12 (2017) C02043
In : Topical Workshop on Electronics for Particle Physics, Karlsruhe, Germany, 26 - 30 Sep 2016, pp.C02043
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