CERN Accelerating science

CERN Document Server Намерени са 2,039 записа  1 - 10следващкрай  отиване на запис: Търсенето отне 6.13 секунди. 
1.
A low-power 10 bit ADC in a 025 mum CMOS : Design considerations and test results / Rivetti, A ; Anelli, G ; Anghinolfi, F ; Mazza, G ; Rotondo, F
This paper presents the design and test of a low power analog to digital converter implemented in a commercial 0.25 mum CMOS technology. The circuit has been developed to serve as a building block in multi-channel data acquisition systems for High Energy Physics (HEP) applications. [...]
2000
In : 47th IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyons, France, 15 - 20 Oct 2000, pp.9/15-9/18 (v.2)
2.
A low-power 10 bit ADC in a 0.25$\mu$m CMOS : design considerations and test results / Rivetti, A ; Anelli, G ; Anghinolfi, Francis ; Mazza, G ; Rotondo, F
This paper presents the design and test of a low power analog to digital converter implemented in a commercial 0.25 mu m CMOS technology. The circuit has been developed to serve as a building block in multi-channel data acquisition systems for high energy physics (HEP) applications. [...]
2000
In : 47th IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyons, France, 15 - 20 Oct 2000, pp.9/15-18 (v.2)
3.
A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology / Anelli, G ; Borer, K ; Casagrande, L ; Despeisse, Matthieu ; Jarron, Pierre ; Pelloux, Nicolas ; Saramad, Shahyar
We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. [...]
2003 - Published in : Nucl. Instrum. Methods Phys. Res., A 512 (2003) 117-128
4.
A large dynamic range radiation tolerant analog memory in a quarter micron CMOS technology / Anelli, G ; Anghinolfi, F ; Rivetti, A
A 8*128 cell analog memory prototype has been designed in a commercial 0.25 jam CMOS process. The aim of this work was to investigate the possibility of designing large dynamic range mixed- mode switched capacitor circuits for High-Energy Physics (HEP) applications in deep submicron CMOS technologies. [...]
2000
In : 47th IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyons, France, 15 - 20 Oct 2000, pp.9/10-9/14 (v.2)
5.
Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments / Anelli, G ; Faccio, F ; Florian, S ; Jarron, Pierre
After having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 mu m CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction at CERN). The 1/f and white noise are studied for n- and p-channel devices with five different gate lengths, in weak, moderate and strong inversion and for different drain to source and bulk to source biases. [...]
Geneva : CERN, 2001 - Published in : Nucl. Instrum. Methods Phys. Res., A 457 (2001) 361-8
6.
Submicron CMOS technologies for high energy physics and space applications / Anelli, G ; Campbell, M ; Faccio, F ; Heijne, Erik H M ; Jarron, Pierre ; Kloukinas, Kostas C ; Marchioro, A ; Moreira, P ; Snoeys, W
The radiation environment present in some of today's High-Energy Physics (HEP) experiments and in space has a detrimental influence on the integrated circuits working in these environments. Special technologies, called radiation hardened, have been used in the past to prevent the radiation-induced degradation. [...]
2001
In : 19th NORCHIP, Kirsta, Sweden, 12 - 13 Nov 2001, pp.59-70
7.
A novel simulation and verification approach in an ASIC design process / Husmann, D ; Keller, M ; Mahboubi, K ; Pfeiffer, U ; Schumacher, C
We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. [...]
2000
In : 47th IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyons, France, 15 - 20 Oct 2000, pp.12/20-4 (v.2)
8.
A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment / Mazza, G ; Rivetti, A ; Anelli, G ; Anghinolfi, F ; Martínez, M I ; Rotondo, F
In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. [...]
2004
In : 50th IEEE 2003 Nuclear Science Symposium, Medical Imaging Conference, 13th International Workshop on Room Temperature Semiconductor Detectors and Symposium on Nuclear Power Systems, Portland, OR, USA, 19 - 25 Oct 2003, pp.391-5 (Vol.1)
9.
A linear laser-driver array for optical transmission in the LHC experiments / Cervelli, G ; Marchioro, A ; Moreira, P ; Vasey, F
A 4-way linear laser driver has been designed and implemented in a commercial 0.25 mu m CMOS technology. The full-custom IC is intended for analogue and digital data transmission as part of the 50 000 optical fibre links of the CMS particle tracking system. [...]
2000
In : 47th IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyons, France, 15 - 20 Oct 2000, pp.9/145-9/149 (v.2)
10.
The APV25 025 mum CMOS readout chip for the CMS tracker / Raymond, M ; French, M ; Fulcher, J R ; Hall, G ; Jones, L ; Kloukinas, K ; Lim, L K ; Marseguerra, G ; Moreira, P ; Morrissey, Q R et al.
The APV25 is a chip designed for readout of silicon microstrips in the CMS tracker at the CERN Large Hadron Collider. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25mum CMOS technology. [...]
2000
In : 47th IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyons, France, 15 - 20 Oct 2000, pp.9/113-9/118 (v.2)

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