PixESL pioneers a virtual prototyping framework for future particle detectors in high-energy physics. Developed at CERN under the EP R&D Work-Package 5, this framework enables high-level abstraction, simulating the full detector chain from particle interaction to data packet readout. It facilitates early optimization of chip and system architecture, which is critical for meeting experiment specifications. PixESL models crucial components such as analog front-end, digital circuitry, and data readout networks, empowering designers to analyze interactions and optimize performance. Leveraging SystemC, PixESL offers rapid simulation runtime and above-RTL abstraction, presenting a pivotal tool for advancing particle detector design and verification.
The high cost of prototyping at advanced technology nodes, as well as the complexity of future detectors, necessitate the use of a system design technique widely used in industry: design space exploration through high-level architecture studies to establish precise and optimal requirements. This work presents Pix-ESL: a programmable SystemC framework for simulating the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, comprises an event generator and connects with real-world physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy. This contribution outlines the framework's structure as well as a case study based on Velopix2.
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