| Начало > Merits of CMOS/SIMOX technology for low-voltage SRAM macros |
| Article | |
| Title | Merits of CMOS/SIMOX technology for low-voltage SRAM macros |
| Author(s) | Kumagai, K ; Iwaki, H ; Yamada, T ; Nakamura, H ; Onishi, H ; Matsubara, Y ; Imai, K ; Kurosawa, S |
| Affiliation | (ULSI Device Dev Labs) |
| Publication | 1999 |
| In: | NEC Res. Dev. 40, 3 (1999) pp.287-91 |
| Abstract | A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs). |