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Article
Title	Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC
Author(s)	Ceesay-Seitz, Katharina (CERN) ; Kundumattathil Mohanan, Sarath (CERN) ; Boukabache, Hamza (CERN) ; Perrin, Daniel (CERN) ; Boukabache, Hamza (CERN)
Publication	2021
Imprint	2021
In:	Design and Verification Conference in Europe, Online, Germany, 26 - 27 Oct 2021
Abstract	This paper details our experience with Formal Property Verification (FPV) of the digital section of a mixed-signal Application Specific Integrated Circuit (ASIC) for ultra-low current measurements. The ASIC was developed as a prototype front-end for the future version of the CERN RadiatiOn Monitoring Electronics (CROME), which is a safety-critical system. The main functionality could be formally proven even though the design contained several counters. A large number of faults could be discovered and removed. The paper aims to demonstrate FPV with SystemVerilog Assertions on a concrete example to give the reader an idea whether and how FPV can be applied to similar designs.
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