002778511 001__ 2778511
002778511 003__ SzGeCERN
002778511 005__ 20220114155545.0
002778511 0247_ $$2DOI$$9JACoW$$a10.18429/JACoW-ICALEPCS2019-MOPHA115
002778511 0248_ $$aoai:cds.cern.ch:2778511$$pcerncds:FULLTEXT$$pcerncds:CERN:FULLTEXT$$pcerncds:CERN
002778511 035__ $$9https://inspirehep.net/api/oai2d$$aoai:inspirehep.net:1827739$$d2021-08-13T11:51:26Z$$h2021-08-14T04:29:52Z$$mmarcxml
002778511 035__ $$9Inspire$$a1827739
002778511 041__ $$aeng
002778511 100__ $$aPlutecki, [email protected]$$uCERN
002778511 245__ $$9JACoW$$aCode Generation Tools and Editor for Memory Maps
002778511 260__ $$c2020
002778511 300__ $$a4 p
002778511 520__ $$9JACoW$$aCheburashka, a toolset created in the Radio Frequency Group at CERN, has become an essential part of our hardware and software developments. Due to changing requirements, this toolset has been recently rewritten in C++ and Python. A hardware developer, using the graphical editor, defines a memory map, which is subsequently used to ensure consistency between software and hardware. The memory map file is an input for a variety of tools used by the hardware engineers, such as VHDL code generators. In addition to aiding the firmware development, our tools generate C++ wrapper libraries. The wrapper provides a simple interface on top of a Linux device driver to read and write registers by exposing memory map nodes in a hierarchical way, performing all low-level bit manipulations and checks internally. To interact with the hardware, a software that runs on a front-end computer is needed. Cheburashka allows us to generate FESA (Front-End Software Architecture) classes with parts of the operational interface already present. This paper describes the evolution of the graphical editor and the Python tools used for C++ code generation, along with a description of their main features.
002778511 540__ $$3publication$$aCC-BY-3.0$$bJACoW$$uhttp://creativecommons.org/licenses/by/3.0/
002778511 542__ $$3publication$$f© JACoW 2019
002778511 65017 $$2SzGeCERN$$aAccelerators and Storage Rings
002778511 6531_ $$2JACoW$$ahardware
002778511 6531_ $$2JACoW$$asoftware
002778511 6531_ $$2JACoW$$ainterface
002778511 6531_ $$2JACoW$$aGUI
002778511 6531_ $$2JACoW$$aLinux
002778511 690C_ $$aARTICLE
002778511 690C_ $$aCERN
002778511 700__ $$aBielawski, Bartosz [email protected]$$uCERN
002778511 700__ $$aButterworth, [email protected]$$uCERN
002778511 773__ $$01827643$$cMOPHA115$$qICALEPCS2019$$wC19-10-05.1$$y2020
002778511 8564_ $$82316267$$s730439$$uhttps://cds.cern.ch/record/2778511/files/10.18429_JACoW-ICALEPCS2019-MOPHA115.pdf$$yFulltext
002778511 960__ $$a13
002778511 962__ $$b2690621$$kMOPHA115$$nnew york20191005
002778511 980__ $$aARTICLE
002778511 980__ $$aConferencePaper