| Published Articles | |
| Title | Real-time reconstruction of pixel vertex detectors with FPGAs |
| Author(s) |
Punzi, Giovanni (INFN, Pisa ; Pisa U.) ; Baldini, Wander (INFN, Ferrara) ; Bassi, Giovanni (INFN, Pisa ; Pisa, Scuola Normale Superiore) ; Contu, Andrea (INFN, Cagliari) ; Dorigo, Mirco (INFN, Trieste) ; Fantechi, Riccardo (INFN, Pisa) ; Lazzari, Federico (INFN, Pisa ; Siena U.) ; Morello, Michael Joseph (INFN, Pisa ; Pisa, Scuola Normale Superiore) ; Stracka, Simone (INFN, Pisa) ; Tuci, Giulia (INFN, Pisa ; Pisa U.) ; Vitali, Giacomo (INFN, Pisa ; Pisa, Scuola Normale Superiore) |
| Publication | SISSA, 2020 |
| Number of pages | 10 |
| In: | PoS Vertex2019 (2020) 047 |
| In: | Vertex 2019: 28th International Workshop on Vertex Detectors, Lopud Island, Croatia, 13 - 18 Oct 2019, pp.047 |
| DOI | 10.22323/1.373.0047 |
| Subject category | Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN LHC ; LHCb |
| Abstract | The LHCb experiment is undergoing a major upgrade in view of Run-3, in which the complete detector will be read out, and events fully reconstructed, at the full LHC crossing rate (averaging 30 MHz). One of the key steps of event reconstruction is finding tracks in the new, high precision pixel vertex detector (VELOPIX). This step is the necessary starting point for most of the rest of the reconstruction, and requires a significant fraction (close to a half) of the total CPU time that will be availabe in the upgraded Event Filter Farm. We present the current status of a LHCb R&D; project devoted to accelerating this computation by the use of an array of commercial state-of- the-art FPGA cards embedded in the DAQ system, performing pattern recognition in the vertex detector ’on the fly’, while the detector is being readout at 30 MHz |
| Copyright/License | © The Authors (License: CC-BY-NC-ND-4.0) |
Corresponding record in: Inspire
Record created 2020-12-12, last modified 2022-11-17
