CERN Accelerating science

Published Articles
Title	Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
Author(s)	Lazzari, Federico (U. Siena (main) ; INFN, Pisa) ; Bassi, Giovanni (INFN, Pisa ; Pisa, Scuola Normale Superiore) ; Cenci, Riccardo (INFN, Pisa ; Pisa, Scuola Normale Superiore) ; Morello, Michael J (INFN, Pisa ; Pisa, Scuola Normale Superiore) ; Punzi, Giovanni (INFN, Pisa ; Pisa U.)
Publication	2020
Number of pages	6
In:	J. Phys.: Conf. Ser. 1525 (2020) 012044
In:	19th International Workshop on Advanced Computing and Analysis Techniques in Physics Research, Saas Fee, Switzerland, 11 - 15 Mar 2019, pp.012044
DOI	10.1088/1742-6596/1525/1/012044
Subject category	Computing and Computers ; Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; LHCb
Abstract	In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.
Copyright/License	© The Authors (License: CC-BY-3.0)

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