CERN Accelerating science

002623947 001__ 2623947
002623947 003__ SzGeCERN
002623947 005__ 20180613225323.0
002623947 0247_ $$2DOI$$9IEEE$$a10.1109/NSSMIC.2016.8069646
002623947 0248_ $$aoai:inspirehep.net:1637907$$pcerncds:CERN$$qINSPIRE:HEP$$qForCDS
002623947 035__ $$9http://inspirehep.net/oai2d$$aoai:inspirehep.net:1637907$$d2018-06-12T18:10:11Z$$h2018-06-13T04:00:08Z$$mmarcxml
002623947 035__ $$9Inspire$$a1637907
002623947 041__ $$aeng
002623947 100__ $$aConti, Elia$$iINSPIRE-00356460$$memail:elia.conti@cern.ch$$uCERN
002623947 245__ $$9IEEE$$aPerformance evaluation of digital pixel readout chip architecture operating at very high rate through a reusable UVM simulation framework
002623947 260__ $$c2017
002623947 300__ $$a4 p
002623947 520__ $$9IEEE$$aA large scale demonstrator pixel readout chip is currently being designed by the RD53 Collaboration, with the goal of proving the suitability of 65 nm technology for the extreme operating conditions associated to the High Luminosity upgrades of the ATLAS and CMS experiments at the Large Hadron Collider. The VEPIX53 simulation and verification environment was developed in order to support the chip design flow at different steps, from architectural modeling and optimization to final design verification, thanks to the flexibility and reusability of System Verilog and the Universal Verification Methodology (UVM) library. In this work a test case of VEPIX53 is presented where an existing digital pixel architecture, already implemented in a small scale prototype chip, is simulated for evaluating whether it satisfies the specifications of the large scale demonstrator chip. The architecture inefficiency was measured by the analysis components of the environment, with respect to different models of analog front-ends and different pixel hit memory sizes, showing possible solutions for optimization.
002623947 65017 $$2SzGeCERN$$aDetectors and Experimental Techniques
002623947 6531_ $$9author$$aMonitoring
002623947 6531_ $$9author$$aPrototypes
002623947 6531_ $$9author$$aLarge Hadron Collider
002623947 6531_ $$9author$$aMonte Carlo methods
002623947 6531_ $$9author$$aComputer architecture
002623947 6531_ $$9author$$aCollaboration
002623947 6531_ $$9author$$aLibraries
002623947 6531_ $$9author$$anuclear electronics
002623947 6531_ $$9author$$aposition sensitive particle detectors
002623947 6531_ $$9author$$areadout electronics
002623947 6531_ $$9author$$aperformance evaluation
002623947 6531_ $$9author$$adigital pixel readout chip architecture
002623947 6531_ $$9author$$areusable UVM simulation framework
002623947 6531_ $$9author$$ascale demonstrator pixel readout chip
002623947 6531_ $$9author$$aRD53 Collaboration
002623947 6531_ $$9author$$aextreme operating conditions
002623947 6531_ $$9author$$aHigh Luminosity upgrades
002623947 6531_ $$9author$$averification environment
002623947 6531_ $$9author$$achip design flow
002623947 6531_ $$9author$$adifferent steps
002623947 6531_ $$9author$$aarchitectural modeling
002623947 6531_ $$9author$$afinal design verification
002623947 6531_ $$9author$$aflexibility
002623947 6531_ $$9author$$areusability
002623947 6531_ $$9author$$aUniversal Verification Methodology library
002623947 6531_ $$9author$$awork a test case
002623947 6531_ $$9author$$aVEPIX53
002623947 6531_ $$9author$$aexisting digital pixel architecture
002623947 6531_ $$9author$$ascale prototype chip
002623947 6531_ $$9author$$ascale demonstrator chip
002623947 6531_ $$9author$$aarchitecture inefficiency
002623947 6531_ $$9author$$adifferent pixel
002623947 6531_ $$9author$$asize 65.0 nm
002623947 690C_ $$aCERN
002623947 693__ $$aNot applicable$$eRD53
002623947 700__ $$aMarconi, Sara$$uINFN, Perugia$$uU. Perugia (main)$$uCERN
002623947 700__ $$aHemperek, Tomasz$$uBonn U.
002623947 700__ $$aChristiansen, J⊘rgen$$uCERN
002623947 700__ $$aPlacidi, Pisana$$uPerugia U.$$uINFN, Perugia
002623947 773__ $$c8069646$$wC16-10-29$$y2016
002623947 960__ $$a13
002623947 962__ $$b2143816$$k8069646$$nstrasbourg20161029
002623947 980__ $$aARTICLE
002623947 980__ $$aConferencePaper
002623947 999C6 $$a0-0-1-1-0-0-0$$t2017-12-05 10:09:09$$vInvenio/1.1.2.1260-aa76f refextract/1.5.44
002623947 999C5 $$9CURATOR$$hJ. Chistiansen, M. Garcia-Sciveres$$o1$$rLHCC-P-006$$tRD Collaboration proposal: Development of pixel readout integrated circuits for extreme rate and radiation$$y2013
002623947 999C5 $$01310836$$hS. Marconi, E. Conti, P. Placidi, J. Christiansen, T. Hemperek$$mThe RD53 Collaboration’s SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips$$o2$$sJINST,9,P10005$$y2014
002623947 999C5 $$01418325$$hE. Conti, S. Marconi, J. Christiansen, P. Placidi, T. Hemperek$$mSimulation of digital pixel readout chip architectures with the RD53 SystemVerilogUVM verification environment using Monte Carlo physics data$$o3$$sJINST,11,C01069$$y2016
002623947 999C5 $$0825736$$hD. Arutinov et al.$$mDigital architecture and interface of the new ATLAS pixel front-end IC for upgraded LHC luminosity$$o4$$sIEEE Trans.Nucl.Sci.,56,388-393$$y2009